153 lines
5.4 KiB
C
153 lines
5.4 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h>
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#include <errno.h>
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#include <string.h>
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#include <assert.h>
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#include <arch_helpers.h>
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#include <platform.h>
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#include <bl_common.h>
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#include <runtime_svc.h>
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#include <context_mgmt.h>
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#include <tspd_private.h>
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/*******************************************************************************
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* Given a secure payload entrypoint, register width, cpu id & pointer to a
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* context data structure, this function will create a secure context ready for
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* programming an entry into the secure payload.
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******************************************************************************/
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int32_t tspd_init_secure_context(uint64_t entrypoint,
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uint32_t rw,
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uint64_t mpidr,
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tsp_context *tsp_ctx)
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{
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uint32_t scr, sctlr;
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el1_sys_regs *el1_state;
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uint32_t spsr;
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/* Passing a NULL context is a critical programming error */
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assert(tsp_ctx);
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/*
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* We support AArch64 TSP for now.
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* TODO: Add support for AArch32 TSP
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*/
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assert(rw == TSP_AARCH64);
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/*
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* This might look redundant if the context was statically
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* allocated but this function cannot make that assumption.
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*/
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memset(tsp_ctx, 0, sizeof(*tsp_ctx));
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/* Set the right security state and register width for the SP */
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scr = read_scr();
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scr &= ~SCR_NS_BIT;
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scr &= ~SCR_RW_BIT;
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if (rw == TSP_AARCH64)
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scr |= SCR_RW_BIT;
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/* Get a pointer to the S-EL1 context memory */
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el1_state = get_sysregs_ctx(&tsp_ctx->cpu_ctx);
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/*
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* Program the SCTLR_EL1 such that upon entry in S-EL1, caches and MMU are
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* disabled and exception endianess is set to be the same as EL3
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*/
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sctlr = read_sctlr_el3()
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sctlr &= SCTLR_EE_BIT;
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sctlr |= SCTLR_EL1_RES1;
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write_ctx_reg(el1_state, CTX_SCTLR_EL1, sctlr);
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/* Set this context as ready to be initialised i.e OFF */
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tsp_ctx->state = TSP_STATE_OFF;
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/* Associate this context with the cpu specified */
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tsp_ctx->mpidr = mpidr;
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cm_set_context(mpidr, &tsp_ctx->cpu_ctx, SECURE);
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spsr = make_spsr(MODE_EL1, MODE_SP_ELX, rw);
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cm_set_el3_eret_context(SECURE, entrypoint, spsr, scr);
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cm_init_exception_stack(mpidr, SECURE);
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return 0;
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}
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/*******************************************************************************
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* This function takes an SP context pointer and:
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* 1. Applies the S-EL1 system register context from tsp_ctx->cpu_ctx.
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* 2. Saves the current C runtime state (callee saved registers) on the stack
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* frame and saves a reference to this state.
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* 3. Calls el3_exit() so that the EL3 system and general purpose registers
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* from the tsp_ctx->cpu_ctx are used to enter the secure payload image.
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******************************************************************************/
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uint64_t tspd_synchronous_sp_entry(tsp_context *tsp_ctx)
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{
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uint64_t rc;
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assert(tsp_ctx->c_rt_ctx == 0);
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/* Apply the Secure EL1 system register context and switch to it */
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assert(cm_get_context(read_mpidr(), SECURE) == &tsp_ctx->cpu_ctx);
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cm_el1_sysregs_context_restore(SECURE);
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cm_set_next_eret_context(SECURE);
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rc = tspd_enter_sp(&tsp_ctx->c_rt_ctx);
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#if DEBUG
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tsp_ctx->c_rt_ctx = 0;
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#endif
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return rc;
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}
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/*******************************************************************************
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* This function takes an SP context pointer and:
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* 1. Saves the S-EL1 system register context tp tsp_ctx->cpu_ctx.
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* 2. Restores the current C runtime state (callee saved registers) from the
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* stack frame using the reference to this state saved in tspd_enter_sp().
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* 3. It does not need to save any general purpose or EL3 system register state
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* as the generic smc entry routine should have saved those.
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******************************************************************************/
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void tspd_synchronous_sp_exit(tsp_context *tsp_ctx, uint64_t ret)
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{
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/* Save the Secure EL1 system register context */
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assert(cm_get_context(read_mpidr(), SECURE) == &tsp_ctx->cpu_ctx);
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cm_el1_sysregs_context_save(SECURE);
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assert(tsp_ctx->c_rt_ctx != 0);
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tspd_exit_sp(tsp_ctx->c_rt_ctx, ret);
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/* Should never reach here */
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assert(0);
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}
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