arm-trusted-firmware/bl31/aarch64
Soby Mathew fdfabec10c Optimize EL3 register state stored in cpu_context structure
This patch further optimizes the EL3 register state stored in
cpu_context. The 2 registers which are removed from cpu_context are:

  * cntfrq_el0 is the system timer register which is writable
    only in EL3 and it can be programmed during cold/warm boot. Hence
    it need not be saved to cpu_context.

  * cptr_el3 controls access to Trace, Floating-point, and Advanced
    SIMD functionality and it is programmed every time during cold
    and warm boot. The current BL3-1 implementation does not need to
    modify the access controls during normal execution and hence
    they are expected to remain static.

Fixes ARM-software/tf-issues#197

Change-Id: I599ceee3b73a7dcfd37069fd41b60e3d397a7b18
2014-07-31 10:09:58 +01:00
..
bl31_arch_setup.c Simplify management of SCTLR_EL3 and SCTLR_EL1 2014-07-28 10:10:22 +01:00
bl31_entrypoint.S Merge pull request #172 from soby-mathew/sm/asm_assert 2014-07-28 14:28:40 +01:00
context.S Optimize EL3 register state stored in cpu_context structure 2014-07-31 10:09:58 +01:00
cpu_data.S Per-cpu data cache restructuring 2014-06-16 21:30:32 +01:00
crash_reporting.S Add CPUECTLR_EL1 and Snoop Control register to crash reporting 2014-07-28 11:03:20 +01:00
runtime_exceptions.S Merge pull request #172 from soby-mathew/sm/asm_assert 2014-07-28 14:28:40 +01:00