080939f924
In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register called "General Control Register0" in the manual rather than the "Cluster 0 Control Register0" in older SoCs. Now the position of AA64nAA32 (reg and bit offset) is defined in a few macros instead assumed to be at bit offset 24 of SUNXI_CPUCFG_CLS_CTRL_REG0. Change-Id: I933d00b9a914bf7103e3a9dadbc6d7be1a409668 Signed-off-by: Icenowy Zheng <icenowy@sipeed.com> |
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.. | ||
include | ||
platform.mk | ||
prepare_dtb.c | ||
sunxi_power.c |