shriram.k d932a5831e feat(plat/arm/sgi): add CPU specific handler for Neoverse N2 ... The 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1' register requires an explicit write to clear it for hotplug and idle to function correctly. So add Neoverse N2 CPU specific handler in platform reset handler to clear the CORE_PWRDN_EN bit. Signed-off-by: shriram.k <shriram.k@arm.com> Change-Id: If3859447410c4b8e704588993941178fa9411f52		2021-09-29 22:47:07 +05:30
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aarch64	feat(plat/arm/sgi): add CPU specific handler for Neoverse N2	2021-09-29 22:47:07 +05:30
include	Merge "plat/sgi: tag dmc620 MM communicate messages with a guid" into integration	2021-07-27 21:35:11 +02:00
sgi-common.mk	feat(plat/sgi): enable use of PSCI extended state ID format	2021-05-27 10:29:17 +05:30
sgi_bl31_setup.c	feat(board/rdn2): add support for variant 1 of rd-n2 platform	2021-04-27 16:29:52 +05:30
sgi_image_load.c	platform/arm/sgi: add multi-chip mode parameter in HW_CONFIG dts	2020-02-07 19:24:17 +05:30
sgi_interconnect.c	Remove several warnings reported with W=1	2019-04-01 10:43:42 +01:00
sgi_plat.c	plat/sgi: allow access to TZC controller on all chips	2021-03-29 21:34:20 +05:30
sgi_plat_v2.c	plat/sgi: allow usage of secure partions on rdn2 platform	2021-03-29 22:00:30 +05:30
sgi_ras.c	fix: avoid redefinition of 'efi_guid' structure	2021-08-06 12:54:11 +01:00
sgi_topology.c	plat/arm/sgi: move topology information to board folder	2020-01-27 19:54:05 +05:30