318 lines
12 KiB
C
318 lines
12 KiB
C
/*
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __MCE_PRIVATE_H__
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#define __MCE_PRIVATE_H__
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#include <mmio.h>
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#include <tegra_def.h>
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/*******************************************************************************
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* Macros to prepare CSTATE info request
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******************************************************************************/
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/* Description of the parameters for UPDATE_CSTATE_INFO request */
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#define CLUSTER_CSTATE_MASK 0x7ULL
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#define CLUSTER_CSTATE_SHIFT 0U
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#define CLUSTER_CSTATE_UPDATE_BIT (1ULL << 7)
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#define CCPLEX_CSTATE_MASK 0x3ULL
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#define CCPLEX_CSTATE_SHIFT 8ULL
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#define CCPLEX_CSTATE_UPDATE_BIT (1ULL << 15)
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#define SYSTEM_CSTATE_MASK 0xFULL
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#define SYSTEM_CSTATE_SHIFT 16ULL
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#define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT 22ULL
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#define SYSTEM_CSTATE_FORCE_UPDATE_BIT (1ULL << 22)
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#define SYSTEM_CSTATE_UPDATE_BIT (1ULL << 23)
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#define CSTATE_WAKE_MASK_UPDATE_BIT (1ULL << 31)
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#define CSTATE_WAKE_MASK_SHIFT 32ULL
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#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFU
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/*******************************************************************************
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* Auto-CC3 control macros
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******************************************************************************/
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#define MCE_AUTO_CC3_FREQ_MASK 0x1FFU
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#define MCE_AUTO_CC3_FREQ_SHIFT 0U
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#define MCE_AUTO_CC3_VTG_MASK 0x7FU
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#define MCE_AUTO_CC3_VTG_SHIFT 16U
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#define MCE_AUTO_CC3_ENABLE_BIT (1U << 31)
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/*******************************************************************************
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* Macros for the 'IS_SC7_ALLOWED' command
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******************************************************************************/
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#define MCE_SC7_ALLOWED_MASK 0x7U
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#define MCE_SC7_WAKE_TIME_SHIFT 32U
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/*******************************************************************************
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* Macros for 'read/write ctats' commands
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******************************************************************************/
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#define MCE_CSTATE_STATS_TYPE_SHIFT 32ULL
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#define MCE_CSTATE_WRITE_DATA_LO_MASK 0xFU
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/*******************************************************************************
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* Macros for 'update crossover threshold' command
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******************************************************************************/
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#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT 32U
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/*******************************************************************************
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* MCA command struct
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******************************************************************************/
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typedef union mca_cmd {
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struct command {
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uint8_t cmd;
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uint8_t idx;
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uint8_t subidx;
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} command;
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struct input {
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uint32_t low;
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uint32_t high;
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} input;
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uint64_t data;
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} mca_cmd_t;
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/*******************************************************************************
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* MCA argument struct
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******************************************************************************/
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typedef union mca_arg {
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struct err {
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uint32_t error:8;
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uint32_t unused:24;
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uint32_t unused2:24;
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uint32_t finish:8;
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} err;
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struct arg {
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uint32_t low;
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uint32_t high;
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} arg;
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uint64_t data;
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} mca_arg_t;
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/*******************************************************************************
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* Uncore PERFMON ARI struct
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******************************************************************************/
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typedef union uncore_perfmon_req {
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struct perfmon_command {
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/*
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* Commands: 0 = READ, 1 = WRITE
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*/
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uint32_t cmd:8;
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/*
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* The unit group: L2=0, L3=1, ROC=2, MC=3, IOB=4
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*/
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uint32_t grp:4;
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/*
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* Unit selector: Selects the unit instance, with 0 = Unit
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* = (number of units in group) - 1.
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*/
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uint32_t unit:4;
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/*
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* Selects the uncore perfmon register to access
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*/
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uint32_t reg:8;
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/*
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* Counter number. Selects which counter to use for
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* registers NV_PMEVCNTR and NV_PMEVTYPER.
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*/
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uint32_t counter:8;
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} perfmon_command;
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struct perfmon_status {
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/*
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* Resulting command status
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*/
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uint32_t val:8;
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uint32_t unused:24;
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} perfmon_status;
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uint64_t data;
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} uncore_perfmon_req_t;
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#define UNCORE_PERFMON_CMD_READ 0U
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#define UNCORE_PERFMON_CMD_WRITE 1U
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#define UNCORE_PERFMON_CMD_MASK 0xFFU
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#define UNCORE_PERFMON_UNIT_GRP_MASK 0xFU
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#define UNCORE_PERFMON_SELECTOR_MASK 0xFU
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#define UNCORE_PERFMON_REG_MASK 0xFFU
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#define UNCORE_PERFMON_CTR_MASK 0xFFU
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#define UNCORE_PERFMON_RESP_STATUS_MASK 0xFFU
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/*******************************************************************************
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* Structure populated by arch specific code to export routines which perform
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* common low level MCE functions
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******************************************************************************/
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typedef struct arch_mce_ops {
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/*
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* This ARI request sets up the MCE to start execution on assertion
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* of STANDBYWFI, update the core power state and expected wake time,
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* then determine the proper power state to enter.
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*/
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int (*enter_cstate)(uint32_t ari_base, uint32_t state,
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uint32_t wake_time);
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/*
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* This ARI request allows updating of the CLUSTER_CSTATE,
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* CCPLEX_CSTATE, and SYSTEM_CSTATE register values.
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*/
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int (*update_cstate_info)(uint32_t ari_base,
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uint32_t cluster,
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uint32_t ccplex,
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uint32_t system,
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uint8_t sys_state_force,
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uint32_t wake_mask,
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uint8_t update_wake_mask);
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/*
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* This ARI request allows updating of power state crossover
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* threshold times. An index value specifies which crossover
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* state is being updated.
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*/
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int (*update_crossover_time)(uint32_t ari_base,
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uint32_t type,
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uint32_t time);
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/*
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* This ARI request allows read access to statistical information
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* related to power states.
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*/
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uint64_t (*read_cstate_stats)(uint32_t ari_base,
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uint32_t state);
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/*
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* This ARI request allows write access to statistical information
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* related to power states.
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*/
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int (*write_cstate_stats)(uint32_t ari_base,
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uint32_t state,
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uint32_t stats);
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/*
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* This ARI request allows the CPU to understand the features
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* supported by the MCE firmware.
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*/
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uint64_t (*call_enum_misc)(uint32_t ari_base, uint32_t cmd,
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uint32_t data);
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/*
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* This ARI request allows querying the CCPLEX to determine if
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* the CCx state is allowed given a target core C-state and wake
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* time. If the CCx state is allowed, the response indicates CCx
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* must be entered. If the CCx state is not allowed, the response
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* indicates CC6/CC7 can't be entered
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*/
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int (*is_ccx_allowed)(uint32_t ari_base, uint32_t state,
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uint32_t wake_time);
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/*
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* This ARI request allows querying the CCPLEX to determine if
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* the SC7 state is allowed given a target core C-state and wake
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* time. If the SC7 state is allowed, all cores but the associated
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* core are offlined (WAKE_EVENTS are set to 0) and the response
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* indicates SC7 must be entered. If the SC7 state is not allowed,
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* the response indicates SC7 can't be entered
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*/
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int (*is_sc7_allowed)(uint32_t ari_base, uint32_t state,
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uint32_t wake_time);
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/*
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* This ARI request allows a core to bring another offlined core
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* back online to the C0 state. Note that a core is offlined by
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* entering a C-state where the WAKE_MASK is all 0.
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*/
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int (*online_core)(uint32_t ari_base, uint32_t cpuid);
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/*
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* This ARI request allows the CPU to enable/disable Auto-CC3 idle
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* state.
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*/
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int (*cc3_ctrl)(uint32_t ari_base,
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uint32_t freq,
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uint32_t volt,
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uint8_t enable);
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/*
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* This ARI request allows updating the reset vector register for
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* D15 and A57 CPUs.
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*/
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int (*update_reset_vector)(uint32_t ari_base);
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/*
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* This ARI request instructs the ROC to flush A57 data caches in
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* order to maintain coherency with the Denver cluster.
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*/
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int (*roc_flush_cache)(uint32_t ari_base);
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/*
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* This ARI request instructs the ROC to flush A57 data caches along
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* with the caches covering ARM code in order to maintain coherency
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* with the Denver cluster.
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*/
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int (*roc_flush_cache_trbits)(uint32_t ari_base);
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/*
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* This ARI request instructs the ROC to clean A57 data caches along
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* with the caches covering ARM code in order to maintain coherency
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* with the Denver cluster.
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*/
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int (*roc_clean_cache)(uint32_t ari_base);
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/*
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* This ARI request reads/writes the Machine Check Arch. (MCA)
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* registers.
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*/
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uint64_t (*read_write_mca)(uint32_t ari_base,
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mca_cmd_t cmd,
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uint64_t *data);
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/*
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* Some MC GSC (General Security Carveout) register values are
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* expected to be changed by TrustZone secure ARM code after boot.
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* Since there is no hardware mechanism for the CCPLEX to know
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* that an MC GSC register has changed to allow it to update its
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* own internal GSC register, there needs to be a mechanism that
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* can be used by ARM code to cause the CCPLEX to update its GSC
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* register value. This ARI request allows updating the GSC register
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* value for a certain carveout in the CCPLEX.
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*/
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int (*update_ccplex_gsc)(uint32_t ari_base, uint32_t gsc_idx);
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/*
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* This ARI request instructs the CCPLEX to either shutdown or
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* reset the entire system
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*/
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void (*enter_ccplex_state)(uint32_t ari_base, uint32_t state_idx);
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/*
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* This ARI request reads/writes data from/to Uncore PERFMON
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* registers
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*/
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int (*read_write_uncore_perfmon)(uint32_t ari_base,
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uncore_perfmon_req_t req, uint64_t *data);
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/*
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* This ARI implements ARI_MISC_CCPLEX commands. This can be
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* used to enable/disable coresight clock gating.
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*/
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void (*misc_ccplex)(uint32_t ari_base, uint32_t index,
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uint32_t value);
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} arch_mce_ops_t;
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/* declarations for ARI/NVG handler functions */
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int ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
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int ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
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uint32_t system, uint8_t sys_state_force, uint32_t wake_mask,
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uint8_t update_wake_mask);
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int ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time);
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uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state);
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int ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats);
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uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data);
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int ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
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int ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
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int ari_online_core(uint32_t ari_base, uint32_t core);
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int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
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int ari_reset_vector_update(uint32_t ari_base);
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int ari_roc_flush_cache_trbits(uint32_t ari_base);
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int ari_roc_flush_cache(uint32_t ari_base);
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int ari_roc_clean_cache(uint32_t ari_base);
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uint64_t ari_read_write_mca(uint32_t ari_base, mca_cmd_t cmd, uint64_t *data);
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int ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx);
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void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx);
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int ari_read_write_uncore_perfmon(uint32_t ari_base,
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uncore_perfmon_req_t req, uint64_t *data);
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void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value);
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int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
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int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
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uint32_t system, uint8_t sys_state_force, uint32_t wake_mask,
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uint8_t update_wake_mask);
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int nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time);
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uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state);
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int nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t val);
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int nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
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int nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
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int nvg_online_core(uint32_t ari_base, uint32_t core);
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int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
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#endif /* __MCE_PRIVATE_H__ */
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