88 lines
2.3 KiB
C
88 lines
2.3 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SOC_CSS_DEF_H__
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#define __SOC_CSS_DEF_H__
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#include <common_def.h>
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#include <utils_def.h>
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/*
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* Definitions common to all ARM CSS SoCs
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*/
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/* Following covers ARM CSS SoC Peripherals and PCIe expansion area */
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#define SOC_CSS_DEVICE_BASE 0x40000000
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#define SOC_CSS_DEVICE_SIZE 0x40000000
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#define SOC_CSS_PCIE_CONTROL_BASE 0x7ff20000
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/* PL011 UART related constants */
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#define SOC_CSS_UART0_BASE 0x7ff80000
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#define SOC_CSS_UART1_BASE 0x7ff70000
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#define SOC_CSS_UART0_CLK_IN_HZ 7372800
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#define SOC_CSS_UART1_CLK_IN_HZ 7372800
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/* SoC NIC-400 Global Programmers View (GPV) */
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#define SOC_CSS_NIC400_BASE 0x7fd00000
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#define SOC_CSS_NIC400_USB_EHCI 0
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#define SOC_CSS_NIC400_TLX_MASTER 1
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#define SOC_CSS_NIC400_USB_OHCI 2
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#define SOC_CSS_NIC400_PL354_SMC 3
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/*
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* The apb4_bridge controls access to:
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* - the PCIe configuration registers
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* - the MMU units for USB, HDLCD and DMA
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*/
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#define SOC_CSS_NIC400_APB4_BRIDGE 4
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/* Non-volatile counters */
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#define SOC_TRUSTED_NVCTR_BASE 0x7fe70000
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#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000)
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#define TFW_NVCTR_SIZE 4
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#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004)
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#define NTFW_CTR_SIZE 4
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/* Keys */
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#define SOC_KEYS_BASE 0x7fe80000
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#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000)
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#define TZ_PUB_KEY_HASH_SIZE 32
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#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020)
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#define HU_KEY_SIZE 16
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#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044)
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#define END_KEY_SIZE 32
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#define SOC_CSS_MAP_DEVICE MAP_REGION_FLAT( \
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SOC_CSS_DEVICE_BASE, \
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SOC_CSS_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/*
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* The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs.
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*/
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#define SOC_CSS_NIC400_BOOTSEC_BRIDGE 5
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#define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 (1 << 12)
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/*
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* Required platform porting definitions common to all ARM CSS SoCs
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*/
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#if JUNO_AARCH32_EL3_RUNTIME
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/*
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* Following change is required to initialize TZC
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* for enabling access to the HI_VECTOR (0xFFFF0000)
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* location needed for JUNO AARCH32 support.
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*/
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#define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x8000)
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#else
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/* 2MB used for SCP DDR retraining */
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#define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x00200000)
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#endif
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#endif /* __SOC_CSS_DEF_H__ */
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