21 lines
665 B
C
21 lines
665 B
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __CORTEX_A35_H__
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#define __CORTEX_A35_H__
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/* Cortex-A35 Main ID register for revision 0 */
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#define CORTEX_A35_MIDR 0x410FD040
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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* CPUECTLR_EL1 is an implementation-specific register.
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******************************************************************************/
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#define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1
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#define CORTEX_A35_CPUECTLR_SMPEN_BIT (1 << 6)
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#endif /* __CORTEX_A35_H__ */
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