409 lines
12 KiB
C
409 lines
12 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <lib/utils.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <mce.h>
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#include <memctrl.h>
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#include <memctrl_v2.h>
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#include <smmu.h>
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#include <tegra_def.h>
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#include <tegra_platform.h>
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/* Video Memory base and size (live values) */
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static uint64_t video_mem_base;
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static uint64_t video_mem_size_mb;
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/*
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* The following platform setup functions are weakly defined. They
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* provide typical implementations that will be overridden by a SoC.
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*/
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#pragma weak plat_memctrl_tzdram_setup
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void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
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{
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; /* do nothing */
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}
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/*
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* Init Memory controller during boot.
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*/
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void tegra_memctrl_setup(void)
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{
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uint32_t val;
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const uint32_t *mc_streamid_override_regs;
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uint32_t num_streamid_override_regs;
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const mc_streamid_security_cfg_t *mc_streamid_sec_cfgs;
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uint32_t num_streamid_sec_cfgs;
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const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
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uint32_t i;
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INFO("Tegra Memory Controller (v2)\n");
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/* Program the SMMU pagesize */
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tegra_smmu_init();
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/* Get the settings from the platform */
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assert(plat_mc_settings != NULL);
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mc_streamid_override_regs = plat_mc_settings->streamid_override_cfg;
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num_streamid_override_regs = plat_mc_settings->num_streamid_override_cfgs;
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mc_streamid_sec_cfgs = plat_mc_settings->streamid_security_cfg;
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num_streamid_sec_cfgs = plat_mc_settings->num_streamid_security_cfgs;
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/* Program all the Stream ID overrides */
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for (i = 0; i < num_streamid_override_regs; i++)
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tegra_mc_streamid_write_32(mc_streamid_override_regs[i],
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MC_STREAM_ID_MAX);
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/* Program the security config settings for all Stream IDs */
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for (i = 0; i < num_streamid_sec_cfgs; i++) {
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val = mc_streamid_sec_cfgs[i].override_enable << 16 |
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mc_streamid_sec_cfgs[i].override_client_inputs << 8 |
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mc_streamid_sec_cfgs[i].override_client_ns_flag << 0;
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tegra_mc_streamid_write_32(mc_streamid_sec_cfgs[i].offset, val);
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}
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/*
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* All requests at boot time, and certain requests during
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* normal run time, are physically addressed and must bypass
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* the SMMU. The client hub logic implements a hardware bypass
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* path around the Translation Buffer Units (TBU). During
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* boot-time, the SMMU_BYPASS_CTRL register (which defaults to
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* TBU_BYPASS mode) will be used to steer all requests around
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* the uninitialized TBUs. During normal operation, this register
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* is locked into TBU_BYPASS_SID config, which routes requests
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* with special StreamID 0x7f on the bypass path and all others
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* through the selected TBU. This is done to disable SMMU Bypass
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* mode, as it could be used to circumvent SMMU security checks.
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*/
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tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG,
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MC_SMMU_BYPASS_CONFIG_SETTINGS);
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/*
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* Re-configure MSS to allow ROC to deal with ordering of the
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* Memory Controller traffic. This is needed as the Memory Controller
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* boots with MSS having all control, but ROC provides a performance
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* boost as compared to MSS.
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*/
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if (plat_mc_settings->reconfig_mss_clients != NULL) {
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plat_mc_settings->reconfig_mss_clients();
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}
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/* Program overrides for MC transactions */
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if (plat_mc_settings->set_txn_overrides != NULL) {
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plat_mc_settings->set_txn_overrides();
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}
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}
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/*
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* Restore Memory Controller settings after "System Suspend"
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*/
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void tegra_memctrl_restore_settings(void)
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{
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const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
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assert(plat_mc_settings != NULL);
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/*
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* Re-configure MSS to allow ROC to deal with ordering of the
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* Memory Controller traffic. This is needed as the Memory Controller
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* resets during System Suspend with MSS having all control, but ROC
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* provides a performance boost as compared to MSS.
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*/
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if (plat_mc_settings->reconfig_mss_clients != NULL) {
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plat_mc_settings->reconfig_mss_clients();
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}
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/* Program overrides for MC transactions */
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if (plat_mc_settings->set_txn_overrides != NULL) {
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plat_mc_settings->set_txn_overrides();
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}
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/* video memory carveout region */
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if (video_mem_base != 0ULL) {
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO,
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(uint32_t)video_mem_base);
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
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(uint32_t)(video_mem_base >> 32));
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tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size_mb);
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/*
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* MCE propagates the VideoMem configuration values across the
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* CCPLEX.
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*/
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mce_update_gsc_videomem();
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}
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}
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/*
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* Secure the BL31 DRAM aperture.
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*
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* phys_base = physical base of TZDRAM aperture
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* size_in_bytes = size of aperture in bytes
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*/
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void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
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{
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/*
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* Perform platform specific steps.
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*/
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plat_memctrl_tzdram_setup(phys_base, size_in_bytes);
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}
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/*
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* Secure the BL31 TZRAM aperture.
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*
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* phys_base = physical base of TZRAM aperture
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* size_in_bytes = size of aperture in bytes
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*/
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void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
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{
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uint32_t index;
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uint32_t total_128kb_blocks = size_in_bytes >> 17;
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uint32_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12;
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uint32_t val;
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INFO("Configuring TrustZone SRAM Memory Carveout\n");
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/*
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* Reset the access configuration registers to restrict access
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* to the TZRAM aperture
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*/
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for (index = MC_TZRAM_CLIENT_ACCESS0_CFG0;
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index < ((uint32_t)MC_TZRAM_CARVEOUT_CFG + (uint32_t)MC_GSC_CONFIG_REGS_SIZE);
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index += 4U) {
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tegra_mc_write_32(index, 0);
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}
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/*
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* Enable CPU access configuration registers to access the TZRAM aperture
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*/
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if (!tegra_chipid_is_t186()) {
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val = tegra_mc_read_32(MC_TZRAM_CLIENT_ACCESS1_CFG0);
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val |= TZRAM_ALLOW_MPCORER | TZRAM_ALLOW_MPCOREW;
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tegra_mc_write_32(MC_TZRAM_CLIENT_ACCESS1_CFG0, val);
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}
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/*
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* Set the TZRAM base. TZRAM base must be 4k aligned, at least.
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*/
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assert((phys_base & (uint64_t)0xFFF) == 0U);
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tegra_mc_write_32(MC_TZRAM_BASE_LO, (uint32_t)phys_base);
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tegra_mc_write_32(MC_TZRAM_BASE_HI,
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(uint32_t)(phys_base >> 32) & MC_GSC_BASE_HI_MASK);
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/*
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* Set the TZRAM size
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*
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* total size = (number of 128KB blocks) + (number of remaining 4KB
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* blocks)
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*
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*/
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val = (residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) |
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total_128kb_blocks;
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tegra_mc_write_32(MC_TZRAM_SIZE, val);
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/*
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* Lock the configuration settings by disabling TZ-only lock
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* and locking the configuration against any future changes
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* at all.
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*/
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val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG);
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val &= (uint32_t)~MC_GSC_ENABLE_TZ_LOCK_BIT;
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val |= MC_GSC_LOCK_CFG_SETTINGS_BIT;
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if (!tegra_chipid_is_t186()) {
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val |= MC_GSC_ENABLE_CPU_SECURE_BIT;
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}
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tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val);
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/*
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* MCE propagates the security configuration values across the
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* CCPLEX.
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*/
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mce_update_gsc_tzram();
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}
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static void tegra_lock_videomem_nonoverlap(uint64_t phys_base,
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uint64_t size_in_bytes)
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{
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uint32_t index;
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uint64_t total_128kb_blocks = size_in_bytes >> 17;
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uint64_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12;
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uint64_t val;
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/*
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* Reset the access configuration registers to restrict access to
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* old Videomem aperture
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*/
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for (index = MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0;
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index < ((uint32_t)MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 + (uint32_t)MC_GSC_CONFIG_REGS_SIZE);
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index += 4U) {
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tegra_mc_write_32(index, 0);
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}
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/*
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* Set the base. It must be 4k aligned, at least.
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*/
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assert((phys_base & (uint64_t)0xFFF) == 0U);
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tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, (uint32_t)phys_base);
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tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI,
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(uint32_t)(phys_base >> 32) & (uint32_t)MC_GSC_BASE_HI_MASK);
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/*
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* Set the aperture size
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*
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* total size = (number of 128KB blocks) + (number of remaining 4KB
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* blocks)
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*
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*/
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val = (uint32_t)((residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) |
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total_128kb_blocks);
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tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, (uint32_t)val);
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/*
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* Lock the configuration settings by enabling TZ-only lock and
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* locking the configuration against any future changes from NS
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* world.
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*/
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tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_CFG,
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(uint32_t)MC_GSC_ENABLE_TZ_LOCK_BIT);
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/*
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* MCE propagates the GSC configuration values across the
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* CCPLEX.
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*/
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}
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static void tegra_unlock_videomem_nonoverlap(void)
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{
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/* Clear the base */
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tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, 0);
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tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI, 0);
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/* Clear the size */
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tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, 0);
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}
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static void tegra_clear_videomem(uintptr_t non_overlap_area_start,
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unsigned long long non_overlap_area_size)
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{
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int ret;
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/*
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* Map the NS memory first, clean it and then unmap it.
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*/
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ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */
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non_overlap_area_start, /* VA */
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non_overlap_area_size, /* size */
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MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */
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assert(ret == 0);
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zero_normalmem((void *)non_overlap_area_start, non_overlap_area_size);
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flush_dcache_range(non_overlap_area_start, non_overlap_area_size);
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(void)mmap_remove_dynamic_region(non_overlap_area_start,
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non_overlap_area_size);
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}
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/*
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* Program the Video Memory carveout region
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*
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* phys_base = physical base of aperture
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* size_in_bytes = size of aperture in bytes
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*/
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void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
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{
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uintptr_t vmem_end_old = video_mem_base + (video_mem_size_mb << 20);
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uintptr_t vmem_end_new = phys_base + size_in_bytes;
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unsigned long long non_overlap_area_size;
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/*
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* Setup the Memory controller to restrict CPU accesses to the Video
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* Memory region
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*/
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INFO("Configuring Video Memory Carveout\n");
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/*
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* Configure Memory Controller directly for the first time.
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*/
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if (video_mem_base == 0U)
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goto done;
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/*
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* Lock the non overlapping memory being cleared so that other masters
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* do not accidently write to it. The memory would be unlocked once
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* the non overlapping region is cleared and the new memory
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* settings take effect.
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*/
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tegra_lock_videomem_nonoverlap(video_mem_base,
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video_mem_size_mb << 20);
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/*
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* Clear the old regions now being exposed. The following cases
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* can occur -
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*
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* 1. clear whole old region (no overlap with new region)
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* 2. clear old sub-region below new base
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* 3. clear old sub-region above new end
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*/
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INFO("Cleaning previous Video Memory Carveout\n");
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if ((phys_base > vmem_end_old) || (video_mem_base > vmem_end_new)) {
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tegra_clear_videomem(video_mem_base,
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video_mem_size_mb << 20U);
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} else {
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if (video_mem_base < phys_base) {
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non_overlap_area_size = phys_base - video_mem_base;
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tegra_clear_videomem(video_mem_base, non_overlap_area_size);
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}
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if (vmem_end_old > vmem_end_new) {
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non_overlap_area_size = vmem_end_old - vmem_end_new;
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tegra_clear_videomem(vmem_end_new, non_overlap_area_size);
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}
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}
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done:
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/* program the Videomem aperture */
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base);
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
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(uint32_t)(phys_base >> 32));
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tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20);
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/* unlock the previous locked nonoverlapping aperture */
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tegra_unlock_videomem_nonoverlap();
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/* store new values */
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video_mem_base = phys_base;
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video_mem_size_mb = size_in_bytes >> 20;
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/*
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* MCE propagates the VideoMem configuration values across the
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* CCPLEX.
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*/
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mce_update_gsc_videomem();
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}
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/*
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* This feature exists only for v1 of the Tegra Memory Controller.
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*/
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void tegra_memctrl_disable_ahb_redirection(void)
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{
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; /* do nothing */
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}
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void tegra_memctrl_clear_pending_interrupts(void)
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{
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; /* do nothing */
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}
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