237 lines
7.0 KiB
C
237 lines
7.0 KiB
C
/*
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* Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <cassert.h>
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#include <common_def.h>
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#include <platform_def.h>
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#include <sys/types.h>
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#include <utils.h>
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#include <xlat_tables.h>
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#include "../xlat_tables_private.h"
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/*
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* Each platform can define the size of the virtual address space, which is
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* defined in PLAT_VIRT_ADDR_SPACE_SIZE. TCR.TxSZ is calculated as 64 minus the
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* width of said address space. The value of TCR.TxSZ must be in the range 16
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* to 39 [1], which means that the virtual address space width must be in the
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* range 48 to 25 bits.
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*
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* Here we calculate the initial lookup level from the value of
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* PLAT_VIRT_ADDR_SPACE_SIZE. For a 4 KB page size, level 0 supports virtual
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* address spaces of widths 48 to 40 bits, level 1 from 39 to 31, and level 2
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* from 30 to 25. Wider or narrower address spaces are not supported. As a
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* result, level 3 cannot be used as initial lookup level with 4 KB
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* granularity. [2]
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*
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* For example, for a 35-bit address space (i.e. PLAT_VIRT_ADDR_SPACE_SIZE ==
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* 1 << 35), TCR.TxSZ will be programmed to (64 - 35) = 29. According to Table
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* D4-11 in the ARM ARM, the initial lookup level for an address space like
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* that is 1.
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*
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* See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
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* information:
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* [1] Page 1730: 'Input address size', 'For all translation stages'.
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* [2] Section D4.2.5
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*/
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#if PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << (64 - TCR_TxSZ_MIN))
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# error "PLAT_VIRT_ADDR_SPACE_SIZE is too big."
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#elif PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << L0_XLAT_ADDRESS_SHIFT)
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# define XLAT_TABLE_LEVEL_BASE 0
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# define NUM_BASE_LEVEL_ENTRIES \
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(PLAT_VIRT_ADDR_SPACE_SIZE >> L0_XLAT_ADDRESS_SHIFT)
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#elif PLAT_VIRT_ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT)
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# define XLAT_TABLE_LEVEL_BASE 1
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# define NUM_BASE_LEVEL_ENTRIES \
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(PLAT_VIRT_ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
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#elif PLAT_VIRT_ADDR_SPACE_SIZE >= (1 << (64 - TCR_TxSZ_MAX))
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# define XLAT_TABLE_LEVEL_BASE 2
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# define NUM_BASE_LEVEL_ENTRIES \
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(PLAT_VIRT_ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT)
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#else
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# error "PLAT_VIRT_ADDR_SPACE_SIZE is too small."
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#endif
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static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES]
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__aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
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static unsigned long long tcr_ps_bits;
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static unsigned long long calc_physical_addr_size_bits(
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unsigned long long max_addr)
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{
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/* Physical address can't exceed 48 bits */
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assert((max_addr & ADDR_MASK_48_TO_63) == 0);
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/* 48 bits address */
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if (max_addr & ADDR_MASK_44_TO_47)
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return TCR_PS_BITS_256TB;
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/* 44 bits address */
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if (max_addr & ADDR_MASK_42_TO_43)
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return TCR_PS_BITS_16TB;
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/* 42 bits address */
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if (max_addr & ADDR_MASK_40_TO_41)
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return TCR_PS_BITS_4TB;
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/* 40 bits address */
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if (max_addr & ADDR_MASK_36_TO_39)
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return TCR_PS_BITS_1TB;
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/* 36 bits address */
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if (max_addr & ADDR_MASK_32_TO_35)
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return TCR_PS_BITS_64GB;
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return TCR_PS_BITS_4GB;
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}
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#if ENABLE_ASSERTIONS
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/* Physical Address ranges supported in the AArch64 Memory Model */
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static const unsigned int pa_range_bits_arr[] = {
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PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100,
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PARANGE_0101
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};
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static unsigned long long get_max_supported_pa(void)
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{
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u_register_t pa_range = read_id_aa64mmfr0_el1() &
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ID_AA64MMFR0_EL1_PARANGE_MASK;
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/* All other values are reserved */
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assert(pa_range < ARRAY_SIZE(pa_range_bits_arr));
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return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL;
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}
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#endif /* ENABLE_ASSERTIONS */
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int xlat_arch_current_el(void)
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{
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int el = GET_EL(read_CurrentEl());
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assert(el > 0);
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return el;
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}
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uint64_t xlat_arch_get_xn_desc(int el)
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{
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if (el == 3) {
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return UPPER_ATTRS(XN);
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} else {
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assert(el == 1);
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return UPPER_ATTRS(PXN);
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}
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}
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void init_xlat_tables(void)
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{
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unsigned long long max_pa;
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uintptr_t max_va;
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print_mmap();
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init_xlation_table(0, base_xlation_table, XLAT_TABLE_LEVEL_BASE,
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&max_va, &max_pa);
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assert(max_va <= PLAT_VIRT_ADDR_SPACE_SIZE - 1);
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assert(max_pa <= PLAT_PHY_ADDR_SPACE_SIZE - 1);
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assert((PLAT_PHY_ADDR_SPACE_SIZE - 1) <= get_max_supported_pa());
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tcr_ps_bits = calc_physical_addr_size_bits(max_pa);
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}
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/*******************************************************************************
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* Macro generating the code for the function enabling the MMU in the given
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* exception level, assuming that the pagetables have already been created.
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*
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* _el: Exception level at which the function will run
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* _tcr_extra: Extra bits to set in the TCR register. This mask will
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* be OR'ed with the default TCR value.
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* _tlbi_fct: Function to invalidate the TLBs at the current
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* exception level
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******************************************************************************/
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#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \
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void enable_mmu_el##_el(unsigned int flags) \
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{ \
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uint64_t mair, tcr, ttbr; \
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uint32_t sctlr; \
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\
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assert(IS_IN_EL(_el)); \
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assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \
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\
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/* Set attributes in the right indices of the MAIR */ \
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mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \
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mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \
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ATTR_IWBWA_OWBWA_NTR_INDEX); \
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mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, \
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ATTR_NON_CACHEABLE_INDEX); \
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write_mair_el##_el(mair); \
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\
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/* Invalidate TLBs at the current exception level */ \
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_tlbi_fct(); \
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\
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/* Set TCR bits as well. */ \
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/* Set T0SZ to (64 - width of virtual address space) */ \
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if (flags & XLAT_TABLE_NC) { \
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/* Inner & outer non-cacheable non-shareable. */\
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tcr = TCR_SH_NON_SHAREABLE | \
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TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC | \
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(64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
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} else { \
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/* Inner & outer WBWA & shareable. */ \
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tcr = TCR_SH_INNER_SHAREABLE | \
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TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA | \
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(64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
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} \
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tcr |= _tcr_extra; \
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write_tcr_el##_el(tcr); \
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\
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/* Set TTBR bits as well */ \
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ttbr = (uint64_t) base_xlation_table; \
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write_ttbr0_el##_el(ttbr); \
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\
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/* Ensure all translation table writes have drained */ \
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/* into memory, the TLB invalidation is complete, */ \
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/* and translation register writes are committed */ \
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/* before enabling the MMU */ \
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dsbish(); \
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isb(); \
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\
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sctlr = read_sctlr_el##_el(); \
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sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \
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\
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if (flags & DISABLE_DCACHE) \
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sctlr &= ~SCTLR_C_BIT; \
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else \
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sctlr |= SCTLR_C_BIT; \
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\
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write_sctlr_el##_el(sctlr); \
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\
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/* Ensure the MMU enable takes effect immediately */ \
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isb(); \
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}
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/* Define EL1 and EL3 variants of the function enabling the MMU */
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DEFINE_ENABLE_MMU_EL(1,
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(tcr_ps_bits << TCR_EL1_IPS_SHIFT),
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tlbivmalle1)
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DEFINE_ENABLE_MMU_EL(3,
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TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT),
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tlbialle3)
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