johpow01 3a2710dcab Workaround for Cortex A78 erratum 1951500 ... Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This workaround works on revisions r1p0 and r1p1, in r0p0 there is no workaround. SDEN can be found here: https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3		2021-01-13 13:54:18 -06:00
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aarch32	Cortex A9:errata 794073 workaround	2019-04-12 10:10:32 +00:00
aarch64	Workaround for Cortex A78 erratum 1951500	2021-01-13 13:54:18 -06:00
cpu-ops.mk	Workaround for Cortex A78 erratum 1951500	2021-01-13 13:54:18 -06:00
errata_report.c	Coverity: remove unnecessary header file includes	2020-02-04 10:23:51 -06:00