65 lines
2.7 KiB
C
65 lines
2.7 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __CORTEX_A72_H__
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#define __CORTEX_A72_H__
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#include <utils_def.h>
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/* Cortex-A72 midr for revision 0 */
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#define CORTEX_A72_MIDR 0x410FD080
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1
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#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
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#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
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#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
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#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
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/*******************************************************************************
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* CPU Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A72_CPUACTLR_EL1 S3_1_C15_C2_0
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#define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
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#define CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55)
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#define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
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#define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
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#define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
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/*******************************************************************************
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* L2 Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0
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#define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN (ULL(1) << 14)
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/*******************************************************************************
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* L2 Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
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#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
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#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
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#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
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/*******************************************************************************
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* L2 Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3
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#endif /* __CORTEX_A72_H__ */
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