164 lines
5.0 KiB
C
164 lines
5.0 KiB
C
/*
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* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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/* Enable the dynamic translation tables library. */
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#ifdef AARCH32
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# if defined(IMAGE_BL32) && RESET_TO_SP_MIN
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# define PLAT_XLAT_TABLES_DYNAMIC 1
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# endif
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#else
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# if defined(IMAGE_BL31) && RESET_TO_BL31
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# define PLAT_XLAT_TABLES_DYNAMIC 1
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# endif
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#endif /* AARCH32 */
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#include <arm_def.h>
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#include <arm_spm_def.h>
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#include <board_arm_def.h>
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#include <common_def.h>
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#include <tzc400.h>
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#include <utils_def.h>
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#include <v2m_def.h>
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#include "../fvp_def.h"
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/* Required platform porting definitions */
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#define PLATFORM_CORE_COUNT \
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(FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU)
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#define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT) + 1
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2
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/*
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* Other platform porting definitions are provided by included headers
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*/
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/*
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* Required ARM standard platform porting definitions
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*/
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#define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT
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#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000
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#define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */
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#define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000
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#define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */
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/* virtual address used by dynamic mem_protect for chunk_base */
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#define PLAT_ARM_MEM_PROTEC_VA_FRAME 0xc0000000
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/* No SCP in FVP */
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#define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x0)
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#define PLAT_ARM_DRAM2_SIZE ULL(0x80000000)
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/*
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* Load address of BL33 for this platform port
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*/
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#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + U(0x8000000))
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/*
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* PL011 related constants
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*/
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#define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE
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#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
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#define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE
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#define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
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#define PLAT_ARM_SP_MIN_RUN_UART_BASE V2M_IOFPGA_UART1_BASE
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#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
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#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE
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#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ
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#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE
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#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ
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#define PLAT_FVP_SMMUV3_BASE 0x2b400000
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/* CCI related constants */
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#define PLAT_FVP_CCI400_BASE 0x2c090000
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#define PLAT_FVP_CCI400_CLUS0_SL_PORT 3
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#define PLAT_FVP_CCI400_CLUS1_SL_PORT 4
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/* CCI-500/CCI-550 on Base platform */
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#define PLAT_FVP_CCI5XX_BASE 0x2a000000
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#define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5
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#define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6
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/* CCN related constants. Only CCN 502 is currently supported */
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#define PLAT_ARM_CCN_BASE 0x2e000000
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#define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11
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/* System timer related constants */
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#define PLAT_ARM_NSTIMER_FRAME_ID 1
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/* Mailbox base address */
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#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
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/* TrustZone controller related constants
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*
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* Currently only filters 0 and 2 are connected on Base FVP.
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* Filter 0 : CPU clusters (no access to DRAM by default)
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* Filter 1 : not connected
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* Filter 2 : LCDs (access to VRAM allowed by default)
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* Filter 3 : not connected
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* Programming unconnected filters will have no effect at the
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* moment. These filter could, however, be connected in future.
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* So care should be taken not to configure the unused filters.
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*
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* Allow only non-secure access to all DRAM to supported devices.
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* Give access to the CPUs and Virtio. Some devices
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* would normally use the default ID so allow that too.
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*/
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#define PLAT_ARM_TZC_BASE 0x2a4a0000
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#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
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#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD))
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/*
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* GIC related constants to cater for both GICv2 and GICv3 instances of an
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* FVP. They could be overriden at runtime in case the FVP implements the legacy
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* VE memory map.
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*/
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#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
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#define PLAT_ARM_GICR_BASE BASE_GICR_BASE
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#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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ARM_G1S_IRQ_PROPS(grp), \
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INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
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#define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS
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#define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS
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#define PLAT_ARM_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \
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ARM_SP_IMAGE_NS_BUF_SIZE)
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#endif /* __PLATFORM_DEF_H__ */
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