154 lines
4.5 KiB
C
154 lines
4.5 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arm_def.h>
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#include <arm_spm_def.h>
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#include <board_arm_def.h>
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#include <board_css_def.h>
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#include <common_def.h>
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#include <css_def.h>
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#include <soc_css_def.h>
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#include <utils_def.h>
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#include <xlat_tables_defs.h>
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#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4
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/* CPU topology */
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#define PLAT_ARM_CLUSTER_COUNT 2
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#define CSS_SGI_MAX_PE_PER_CPU 1
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#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \
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CSS_SGI_MAX_CPUS_PER_CLUSTER * \
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CSS_SGI_MAX_PE_PER_CPU)
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#if ARM_BOARD_OPTIMISE_MEM
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#if defined(IMAGE_BL31) || defined(IMAGE_BL32)
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# define PLAT_ARM_MMAP_ENTRIES 6
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# define MAX_XLAT_TABLES 4
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#else
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# define PLAT_ARM_MMAP_ENTRIES 10
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# define MAX_XLAT_TABLES 5
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#endif
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#if TRUSTED_BOARD_BOOT
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# define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000
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#else
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# define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000
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#endif
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#if TRUSTED_BOARD_BOOT
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# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
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#else
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# define PLAT_ARM_MAX_BL2_SIZE 0xC000
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#endif
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#endif /* ARM_BOARD_OPTIMISE_MEM */
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#define PLAT_ARM_NSTIMER_FRAME_ID 0
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#define PLAT_CSS_MHU_BASE 0x45000000
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#define PLAT_ARM_TRUSTED_ROM_BASE 0x0
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#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */
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#define PLAT_ARM_NSRAM_BASE 0x06000000
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#define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */
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#define PLAT_MAX_PWR_LVL U(1)
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
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#define CSS_SGI_DEVICE_BASE (0x20000000)
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#define CSS_SGI_DEVICE_SIZE (0x20000000)
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#define CSS_SGI_MAP_DEVICE MAP_REGION_FLAT( \
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CSS_SGI_DEVICE_BASE, \
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CSS_SGI_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/* GIC related constants */
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#define PLAT_ARM_GICD_BASE 0x30000000
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#define PLAT_ARM_GICC_BASE 0x2C000000
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#define PLAT_ARM_GICR_BASE 0x300C0000
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/* Map the secure region for access from S-EL0 */
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#define PLAT_ARM_SECURE_MAP_DEVICE MAP_REGION_FLAT( \
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SOC_CSS_DEVICE_BASE, \
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SOC_CSS_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
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#if RAS_EXTENSION
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/* Allocate 128KB for CPER buffers */
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#define PLAT_SP_BUF_BASE ULL(0x20000)
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#define PLAT_ARM_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \
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ARM_SP_IMAGE_NS_BUF_SIZE + \
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PLAT_SP_BUF_BASE)
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/* Platform specific SMC FID's used for RAS */
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#define SP_DMC_ERROR_INJECT_EVENT_AARCH64 0xC4000042
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#define SP_DMC_ERROR_INJECT_EVENT_AARCH32 0x84000042
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#define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH64 0xC4000043
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#define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH32 0x84000043
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#define SP_DMC_ERROR_ECC_EVENT_AARCH64 0xC4000044
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#define SP_DMC_ERROR_ECC_EVENT_AARCH32 0x84000044
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/* ARM SDEI dynamic shared event numbers */
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#define SGI_SDEI_DS_EVENT_0 804
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#define SGI_SDEI_DS_EVENT_1 805
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#define PLAT_ARM_PRIVATE_SDEI_EVENTS \
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SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \
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SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_0, SDEI_MAPF_CRITICAL), \
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SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_1, SDEI_MAPF_CRITICAL),
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#define PLAT_ARM_SHARED_SDEI_EVENTS
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#define ARM_SP_CPER_BUF_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \
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ARM_SP_IMAGE_NS_BUF_SIZE)
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#define ARM_SP_CPER_BUF_SIZE ULL(0x20000)
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#define ARM_SP_CPER_BUF_MMAP MAP_REGION2( \
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ARM_SP_CPER_BUF_BASE, \
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ARM_SP_CPER_BUF_BASE, \
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ARM_SP_CPER_BUF_SIZE, \
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MT_RW_DATA | MT_NS | MT_USER, \
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PAGE_SIZE)
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#else
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#define PLAT_ARM_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \
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ARM_SP_IMAGE_NS_BUF_SIZE)
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#endif /* RAS_EXTENSION */
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/* Platform ID address */
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#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
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#ifndef __ASSEMBLY__
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/* SSC_VERSION related accessors */
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/* Returns the part number of the platform */
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#define GET_SGI_PART_NUM \
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GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION))
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/* Returns the configuration number of the platform */
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#define GET_SGI_CONFIG_NUM \
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GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION))
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#endif /* __ASSEMBLY__ */
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/*******************************************************************************
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* Memprotect definitions
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******************************************************************************/
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/* PSCI memory protect definitions:
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* This variable is stored in a non-secure flash because some ARM reference
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* platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
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* support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
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*/
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#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
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V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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#endif /* PLATFORM_DEF_H */
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