Hadi Asyrafi 3dcb94dd84 intel: Enable bridge access in Intel platform ... Add bridge enablement features for each platform. The bridge access will be enabled automatically for FPGA 1st configuration only. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f		2020-01-16 10:53:21 +08:00
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s10_clock_manager.h	intel: Refactor common platform code [1/5]	2019-11-28 12:47:57 +08:00
s10_memory_controller.h	intel: Enable bridge access in Intel platform	2020-01-16 10:53:21 +08:00
s10_noc.h	plat: intel: Add BL2 support for Stratix 10 SoC	2019-02-04 16:17:24 +08:00
s10_pinmux.h	intel: Refactor common platform code [1/5]	2019-11-28 12:47:57 +08:00
s10_reset_manager.h	intel: Enable bridge access in Intel platform	2020-01-16 10:53:21 +08:00
s10_system_manager.h	intel: Enable bridge access in Intel platform	2020-01-16 10:53:21 +08:00
socfpga_plat_def.h	intel: Refactor common platform code [1/5]	2019-11-28 12:47:57 +08:00