johpow01 62bbfe82c8 Workaround for Cortex A77 erratum 1800714 ... Cortex A77 erratum 1800714 is a Cat B erratum, present in older revisions of the Cortex A77 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. Since this is the first errata workaround implemented for Cortex A77, this patch also adds the required cortex_a77_reset_func in the file lib/cpus/aarch64/cortex_a77.S. This errata is explained in this SDEN: https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I844de34ee1bd0268f80794e2d9542de2f30fd3ad		2020-06-25 14:50:58 +00:00
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arch	Prevent RAS register access from lower ELs	2020-06-12 10:20:11 -07:00
bl1	coverity: fix MISRA violations	2020-02-18 10:47:46 -06:00
bl2	BL2_AT_EL3: Enable pointer authentication support	2019-02-27 11:58:09 +00:00
bl2u	Standardise header guards across codebase	2018-11-08 10:20:19 +00:00
bl31	Use correct type when reading SCR register	2020-01-28 11:10:48 +00:00
bl32	spd: tlkd: support new TLK SMCs for RPMB service	2020-03-21 19:00:05 -07:00
common	dualroot: add chain of trust for secure partitions	2020-06-09 16:22:26 +01:00
drivers	Merge "TF-A GIC driver: Add barrier before eoi" into integration	2020-06-22 19:57:52 +00:00
dt-bindings	drivers: introduce ST ETZPC driver	2020-06-03 15:53:46 +02:00
export	dualroot: add chain of trust for secure partitions	2020-06-09 16:22:26 +01:00
lib	Workaround for Cortex A77 erratum 1800714	2020-06-25 14:50:58 +00:00
plat	Merge changes I80316689,I23cac4fb,If911e7de,I169ff358,I4e040cd5, ... into integration	2020-06-17 19:44:51 +00:00
services	FFA Version interface update	2020-06-23 15:08:48 +01:00
tools_share	cert_create: extend Secure partition support for tbbr CoT	2020-06-11 23:13:09 +01:00