33 lines
1.1 KiB
C
33 lines
1.1 KiB
C
/*
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* Copyright (c) 2022, Google LLC. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_X1_H
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#define CORTEX_X1_H
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/* Cortex-X1 MIDR for r1p0 */
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#define CORTEX_X1_MIDR U(0x411fd440)
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/* Cortex-X1 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_X1_BHB_LOOP_COUNT U(32)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_X1_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_X1_ACTLR2_EL1 S3_0_C15_C1_1
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_X1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_X1_CORE_PWRDN_EN_MASK U(0x1)
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#endif /* CORTEX_X1_H */
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