343 lines
10 KiB
C
343 lines
10 KiB
C
/*
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* Copyright (c) 2019, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <common/tbbr/tbbr_img_def.h>
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#include <lib/utils_def.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#include <plat/arm/board/common/v2m_def.h>
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#include <plat/common/common_def.h>
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#include "../fvp_ve_def.h"
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#define ARM_CACHE_WRITEBACK_SHIFT 6
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/* Memory location options for TSP */
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#define ARM_DRAM_ID 2
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#define ARM_DRAM1_BASE UL(0x80000000)
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#define ARM_DRAM1_SIZE UL(0x80000000)
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#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
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ARM_DRAM1_SIZE - 1)
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#define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE
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#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
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#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
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ARM_DRAM2_SIZE - 1)
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#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
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/*
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* The last 2MB is meant to be NOLOAD and will not be zero
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* initialized.
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*/
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#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
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0x00200000)
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/* The first 4KB of NS DRAM1 are used as shared memory */
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#define FVP_VE_SHARED_RAM_BASE ARM_NS_DRAM1_BASE
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#define FVP_VE_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */
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/* The next 252 kB of NS DRAM is used to load the BL images */
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#define ARM_BL_RAM_BASE (FVP_VE_SHARED_RAM_BASE + \
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FVP_VE_SHARED_RAM_SIZE)
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#define ARM_BL_RAM_SIZE (PLAT_ARM_BL_PLUS_SHARED_RAM_SIZE - \
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FVP_VE_SHARED_RAM_SIZE)
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#define ARM_IRQ_SEC_PHY_TIMER 29
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#define ARM_IRQ_SEC_SGI_0 8
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#define ARM_IRQ_SEC_SGI_1 9
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#define ARM_IRQ_SEC_SGI_2 10
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#define ARM_IRQ_SEC_SGI_3 11
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#define ARM_IRQ_SEC_SGI_4 12
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#define ARM_IRQ_SEC_SGI_5 13
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#define ARM_IRQ_SEC_SGI_6 14
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#define ARM_IRQ_SEC_SGI_7 15
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/*
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* Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define ARM_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_EDGE)
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#define ARM_G0_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_EDGE)
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#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
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FVP_VE_SHARED_RAM_BASE, \
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FVP_VE_SHARED_RAM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
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ARM_NS_DRAM1_BASE, \
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ARM_NS_DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \
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ARM_DRAM2_BASE, \
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ARM_DRAM2_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
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BL_CODE_BASE, \
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BL_CODE_END - BL_CODE_BASE, \
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MT_CODE | MT_SECURE), \
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MAP_REGION_FLAT( \
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BL_RO_DATA_BASE, \
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BL_RO_DATA_END \
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- BL_RO_DATA_BASE, \
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MT_RO_DATA | MT_SECURE)
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#if USE_COHERENT_MEM
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#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
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BL_COHERENT_RAM_BASE, \
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BL_COHERENT_RAM_END \
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- BL_COHERENT_RAM_BASE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#endif
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/*
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* The max number of regions like RO(code), coherent and data required by
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* different BL stages which need to be mapped in the MMU.
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*/
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#define ARM_BL_REGIONS 5
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#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
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ARM_BL_REGIONS)
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/* Memory mapped Generic timer interfaces */
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#define FVP_VE_TIMER_BASE_FREQUENCY UL(24000000)
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#define ARM_SYS_CNTREAD_BASE UL(0x2a800000)
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#define ARM_SYS_CNT_BASE_S UL(0x2a820000)
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#define ARM_SYS_CNT_BASE_NS UL(0x2a830000)
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#define ARM_CONSOLE_BAUDRATE 115200
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/* Trusted Watchdog constants */
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#define ARM_SP805_TWDG_BASE UL(0x1C0F0000)
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#define ARM_SP805_TWDG_CLK_HZ 32768
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/* The TBBR document specifies a watchdog timeout of 256 seconds. SP805
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* asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */
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#define ARM_TWDG_TIMEOUT_SEC 128
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#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \
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ARM_TWDG_TIMEOUT_SEC)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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/*
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* This macro defines the deepest retention state possible. A higher state
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* id will represent an invalid or a power down state.
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*/
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#define PLAT_MAX_RET_STATE 1
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/*
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* This macro defines the deepest power down states possible. Any state ID
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* higher than this is invalid.
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*/
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#define PLAT_MAX_OFF_STATE 2
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
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/*
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* To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base
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* and limit. Leave enough space of BL2 meminfo.
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*/
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#define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
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#define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE)
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/*******************************************************************************
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* BL1 specific defines.
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* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
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* addresses.
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******************************************************************************/
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#define BL1_RO_BASE 0x00000000
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#define BL1_RO_LIMIT PLAT_ARM_TRUSTED_ROM_SIZE
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/*
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* Put BL1 RW at the top of the memory allocated for BL images in NS DRAM.
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*/
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#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
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ARM_BL_RAM_SIZE - \
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(PLAT_ARM_MAX_BL1_RW_SIZE))
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#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \
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(ARM_BL_RAM_SIZE))
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/*******************************************************************************
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* BL2 specific defines.
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******************************************************************************/
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/*
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* Put BL2 just below BL1.
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*/
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#define BL2_BASE (BL1_RW_BASE - FVP_VE_MAX_BL2_SIZE)
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#define BL2_LIMIT BL1_RW_BASE
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/* Put BL32 below BL2 in NS DRAM.*/
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#define ARM_BL2_MEM_DESC_BASE ARM_TB_FW_CONFIG_LIMIT
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#define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
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- PLAT_ARM_MAX_BL32_SIZE)
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#define BL32_PROGBITS_LIMIT BL2_BASE
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#define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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/* Required platform porting definitions */
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#define PLATFORM_CORE_COUNT 1
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#define PLAT_NUM_PWR_DOMAINS ((FVP_VE_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT) + 1)
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#define PLAT_MAX_PWR_LVL 2
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/*
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* Other platform porting definitions are provided by included headers
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*/
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/*
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* Required ARM standard platform porting definitions
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*/
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#define PLAT_ARM_BL_PLUS_SHARED_RAM_SIZE 0x00040000 /* 256 KB */
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#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000
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#define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */
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#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
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#define PLAT_ARM_DRAM2_SIZE ULL(0x80000000)
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/*
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* Load address of BL33 for this platform port
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*/
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#define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + U(0x8000000))
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/*
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* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
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* plat_arm_mmap array defined for each BL stage.
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*/
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#if defined(IMAGE_BL32)
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# define PLAT_ARM_MMAP_ENTRIES 8
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# define MAX_XLAT_TABLES 6
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#else
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# define PLAT_ARM_MMAP_ENTRIES 12
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# define MAX_XLAT_TABLES 6
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#endif
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/*
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* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
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* plus a little space for growth.
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*/
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#define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000
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/*
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* FVP_VE_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
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* little space for growth.
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*/
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#define FVP_VE_MAX_BL2_SIZE 0x11000
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/*
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* Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is
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* calculated using the current SP_MIN PROGBITS debug size plus the sizes of
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* BL2 and BL1-RW
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*/
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#define PLAT_ARM_MAX_BL32_SIZE 0x3B000
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/*
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* Size of cacheable stacks
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*/
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#if defined(IMAGE_BL1)
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# define PLATFORM_STACK_SIZE 0x440
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#elif defined(IMAGE_BL2)
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# define PLATFORM_STACK_SIZE 0x400
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#elif defined(IMAGE_BL32)
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# define PLATFORM_STACK_SIZE 0x440
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#endif
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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/* Reserve the last block of flash for PSCI MEM PROTECT flag */
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#define PLAT_ARM_FIP_BASE V2M_FLASH1_BASE
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#define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
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#define PLAT_ARM_NVM_BASE V2M_FLASH1_BASE
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#define PLAT_ARM_NVM_SIZE (V2M_FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
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/*
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* PL011 related constants
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*/
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#define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE
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#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
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#define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE
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#define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
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#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
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#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
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/* System timer related constants */
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#define PLAT_ARM_NSTIMER_FRAME_ID 1
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/* Mailbox base address */
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#define FVP_VE_TRUSTED_MAILBOX_BASE FVP_VE_SHARED_RAM_BASE
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/*
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* GIC related constants to cater for GICv2
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*/
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#define PLAT_ARM_GICD_BASE VE_GICD_BASE
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#define PLAT_ARM_GICC_BASE VE_GICC_BASE
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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ARM_G1S_IRQ_PROPS(grp), \
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INTR_PROP_DESC(FVP_VE_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(FVP_VE_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_LEVEL)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
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/*
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* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
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*/
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#ifdef __aarch64__
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
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#else
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#endif
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#endif /* PLATFORM_H */
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