116 lines
3.4 KiB
C
116 lines
3.4 KiB
C
/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <plat/arm/board/common/v2m_def.h>
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#include <plat/arm/common/arm_def.h>
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#include <plat/arm/css/common/css_def.h>
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/* UART related constants */
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#define PLAT_ARM_BOOT_UART_BASE 0x2A400000
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#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 50000000
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#define PLAT_ARM_RUN_UART_BASE 0x2A410000
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#define PLAT_ARM_RUN_UART_CLK_IN_HZ 50000000
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#define PLAT_ARM_SP_MIN_RUN_UART_BASE 0x2A410000
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#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ 50000000
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#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
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#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
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#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
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#define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000)
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/*
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* N1SDP platform supports RDIMMs with ECC capability. To use the ECC
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* capability, the entire DDR memory space has to be zeroed out before
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* enabling the ECC bits in DMC620. The access the complete DDR memory
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* space the physical & virtual address space limits are extended to
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* 40-bits.
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*/
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#ifdef __aarch64__
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40)
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#else
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#endif
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#if CSS_USE_SCMI_SDS_DRIVER
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#define N1SDP_SCMI_PAYLOAD_BASE 0x45400000
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#else
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#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000
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#endif
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#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */
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#define PLAT_ARM_MAX_BL31_SIZE 0X20000
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/*******************************************************************************
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* N1SDP topology related constants
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******************************************************************************/
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#define N1SDP_MAX_CPUS_PER_CLUSTER 2
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#define PLAT_ARM_CLUSTER_COUNT 2
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#define N1SDP_MAX_PE_PER_CPU 1
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#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \
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N1SDP_MAX_CPUS_PER_CLUSTER * \
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N1SDP_MAX_PE_PER_CPU)
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/* System power domain level */
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
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/*
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* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
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* plat_arm_mmap array defined for each BL stage.
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*/
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#define PLAT_ARM_MMAP_ENTRIES 6
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#define MAX_XLAT_TABLES 7
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#define PLATFORM_STACK_SIZE 0x400
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#define PLAT_ARM_NSTIMER_FRAME_ID 0
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#define PLAT_CSS_MHU_BASE 0x45000000
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#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
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#define PLAT_MAX_PWR_LVL 1
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#define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \
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CSS_IRQ_MHU
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#define PLAT_ARM_G0_IRQS ARM_G0_IRQS
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
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#define N1SDP_DEVICE_BASE (0x08000000)
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#define N1SDP_DEVICE_SIZE (0x48000000)
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#define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \
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N1SDP_DEVICE_BASE, \
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N1SDP_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define ARM_MAP_DRAM1 MAP_REGION_FLAT( \
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ARM_DRAM1_BASE, \
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ARM_DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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/* GIC related constants */
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#define PLAT_ARM_GICD_BASE 0x30000000
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#define PLAT_ARM_GICC_BASE 0x2C000000
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#define PLAT_ARM_GICR_BASE 0x300C0000
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/* Platform ID address */
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#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
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/* Secure Watchdog Constants */
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#define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
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#define SBSA_SECURE_WDOG_TIMEOUT UL(100)
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#endif /* PLATFORM_DEF_H */
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