40a0de1972
The Statistical Profiling Extension (SPE) is an architectural feature we can safely detect at runtime. However it still relies on one piece of platform-specific information: the interrupt line it is connected to. This requires SPE to be described in a devicetree node. Since SPE support varies with the CPU cores found on an FPGA image, we should detect the presence of SPE at runtime, and remove a potentially existing SPE PMU node from the DT. This allows to always have the SPE node in a generic devicetree file, without risking exposing it on a CPU without this feature. Change-Id: I73d83ea8509b03fe7bba20b9cce8d1335035fa31 Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
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| a5ds | ||
| arm_fpga | ||
| common | ||
| corstone700 | ||
| fvp | ||
| fvp_ve | ||
| juno | ||
| n1sdp | ||
| rddaniel | ||
| rddanielxlr | ||
| rde1edge | ||
| rdn1edge | ||
| sgi575 | ||
| sgm775 | ||
| tc0 | ||