247 lines
6.8 KiB
C
247 lines
6.8 KiB
C
/*
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* Copyright (c) 2018-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <plat/arm/board/common/v2m_def.h>
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#include <plat/arm/common/arm_def.h>
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#include <plat/arm/css/common/css_def.h>
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/* UART related constants */
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#define PLAT_ARM_BOOT_UART_BASE 0x2A400000
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#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 50000000
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#define PLAT_ARM_RUN_UART_BASE 0x2A410000
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#define PLAT_ARM_RUN_UART_CLK_IN_HZ 50000000
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#define PLAT_ARM_SP_MIN_RUN_UART_BASE 0x2A410000
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#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ 50000000
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#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
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#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
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#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
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#define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000)
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#define MAX_IO_DEVICES U(3)
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#define MAX_IO_HANDLES U(4)
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#define PLAT_ARM_FLASH_IMAGE_BASE 0x18200000
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#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE 0x00800000
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#define PLAT_ARM_NVM_BASE 0x18200000
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#define PLAT_ARM_NVM_SIZE 0x00800000
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#if defined NS_BL1U_BASE
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# undef NS_BL1U_BASE
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# define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x00800000))
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#endif
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/* Non-volatile counters */
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#define SOC_TRUSTED_NVCTR_BASE 0x7fe70000
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#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE)
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#define TFW_NVCTR_SIZE U(4)
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#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004)
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#define NTFW_CTR_SIZE U(4)
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/* N1SDP remote chip at 4 TB offset */
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#define PLAT_ARM_REMOTE_CHIP_OFFSET (ULL(1) << 42)
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#define N1SDP_REMOTE_DRAM1_BASE ARM_DRAM1_BASE + \
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PLAT_ARM_REMOTE_CHIP_OFFSET
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#define N1SDP_REMOTE_DRAM1_SIZE ARM_DRAM1_SIZE
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#define N1SDP_REMOTE_DRAM2_BASE PLAT_ARM_DRAM2_BASE + \
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PLAT_ARM_REMOTE_CHIP_OFFSET
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#define N1SDP_REMOTE_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
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/*
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* N1SDP platform supports RDIMMs with ECC capability. To use the ECC
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* capability, the entire DDR memory space has to be zeroed out before
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* enabling the ECC bits in DMC620. To access the complete DDR memory
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* along with remote chip's DDR memory, which is at 4 TB offset, physical
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* and virtual address space limits are extended to 43-bits.
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*/
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#ifdef __aarch64__
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 43)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 43)
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#else
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#endif
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#if CSS_USE_SCMI_SDS_DRIVER
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#define N1SDP_SCMI_PAYLOAD_BASE 0x45400000
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#else
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#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000
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#endif
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/*
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* Trusted SRAM in N1SDP is 512 KB but only the bottom 384 KB
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* is used for trusted board boot flow. The top 128 KB is used
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* to load AP-BL1 image.
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*/
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#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00060000 /* 384 KB */
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/*
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* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
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* plus a little space for growth.
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*/
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#define PLAT_ARM_MAX_BL1_RW_SIZE 0xE000
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/*
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* PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
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*/
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#if USE_ROMLIB
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# define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000
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# define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000
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#else
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# define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0)
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# define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0)
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#endif
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/*
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* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
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* little space for growth.
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*/
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#if TRUSTED_BOARD_BOOT
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# define PLAT_ARM_MAX_BL2_SIZE 0x20000
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#else
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# define PLAT_ARM_MAX_BL2_SIZE 0x14000
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#endif
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#define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000)
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/*******************************************************************************
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* N1SDP topology related constants
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******************************************************************************/
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#define N1SDP_MAX_CPUS_PER_CLUSTER U(2)
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#define PLAT_ARM_CLUSTER_COUNT U(2)
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#define PLAT_N1SDP_CHIP_COUNT U(2)
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#define N1SDP_MAX_CLUSTERS_PER_CHIP U(2)
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#define N1SDP_MAX_PE_PER_CPU U(1)
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#define PLATFORM_CORE_COUNT (PLAT_N1SDP_CHIP_COUNT * \
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PLAT_ARM_CLUSTER_COUNT * \
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N1SDP_MAX_CPUS_PER_CLUSTER * \
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N1SDP_MAX_PE_PER_CPU)
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/* System power domain level */
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3
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/*
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* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
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* plat_arm_mmap array defined for each BL stage.
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*/
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#ifdef IMAGE_BL1
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# define PLAT_ARM_MMAP_ENTRIES U(6)
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# define MAX_XLAT_TABLES U(5)
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#endif
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#ifdef IMAGE_BL2
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# define PLAT_ARM_MMAP_ENTRIES U(11)
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# define MAX_XLAT_TABLES U(10)
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#endif
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#ifdef IMAGE_BL31
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# define PLAT_ARM_MMAP_ENTRIES U(12)
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# define MAX_XLAT_TABLES U(12)
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#endif
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/*
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* Size of cacheable stacks
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*/
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#if defined(IMAGE_BL1)
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# if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE 0x1000
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# else
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# define PLATFORM_STACK_SIZE 0x440
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# endif
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#elif defined(IMAGE_BL2)
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# if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE 0x1000
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# else
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# define PLATFORM_STACK_SIZE 0x400
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# endif
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#elif defined(IMAGE_BL2U)
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# define PLATFORM_STACK_SIZE 0x400
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#elif defined(IMAGE_BL31)
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# if SPM_MM
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# define PLATFORM_STACK_SIZE 0x500
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# else
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# define PLATFORM_STACK_SIZE 0x400
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# endif
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#elif defined(IMAGE_BL32)
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# define PLATFORM_STACK_SIZE 0x440
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#endif
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#define PLAT_ARM_NSTIMER_FRAME_ID 0
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#define PLAT_CSS_MHU_BASE 0x45000000
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#define PLAT_MAX_PWR_LVL 2
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#define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \
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CSS_IRQ_MHU
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#define PLAT_ARM_G0_IRQS ARM_G0_IRQS
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
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#define N1SDP_DEVICE_BASE ULL(0x08000000)
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#define N1SDP_DEVICE_SIZE ULL(0x48000000)
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#define N1SDP_REMOTE_DEVICE_BASE N1SDP_DEVICE_BASE + \
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PLAT_ARM_REMOTE_CHIP_OFFSET
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#define N1SDP_REMOTE_DEVICE_SIZE N1SDP_DEVICE_SIZE
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/* Real base is 0x0. Changed to load BL1 at this address */
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# define PLAT_ARM_TRUSTED_ROM_BASE 0x04060000
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# define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 /* 128KB */
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#define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \
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N1SDP_DEVICE_BASE, \
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N1SDP_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define ARM_MAP_DRAM1 MAP_REGION_FLAT( \
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ARM_DRAM1_BASE, \
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ARM_DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define N1SDP_MAP_REMOTE_DEVICE MAP_REGION_FLAT( \
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N1SDP_REMOTE_DEVICE_BASE, \
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N1SDP_REMOTE_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define N1SDP_MAP_REMOTE_DRAM1 MAP_REGION_FLAT( \
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N1SDP_REMOTE_DRAM1_BASE, \
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N1SDP_REMOTE_DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define N1SDP_MAP_REMOTE_DRAM2 MAP_REGION_FLAT( \
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N1SDP_REMOTE_DRAM2_BASE, \
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N1SDP_REMOTE_DRAM2_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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/* GIC related constants */
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#define PLAT_ARM_GICD_BASE 0x30000000
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#define PLAT_ARM_GICC_BASE 0x2C000000
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#define PLAT_ARM_GICR_BASE 0x300C0000
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/* Platform ID address */
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#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
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/* Secure Watchdog Constants */
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#define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
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#define SBSA_SECURE_WDOG_TIMEOUT UL(100)
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/* Number of SCMI channels on the platform */
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#define PLAT_ARM_SCMI_CHANNEL_COUNT U(1)
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#endif /* PLATFORM_DEF_H */
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