53 lines
1.6 KiB
C
53 lines
1.6 KiB
C
/*
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* Copyright (c) 2018-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef N1SDP_DEF_H
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#define N1SDP_DEF_H
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/* Non-secure SRAM MMU mapping */
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#define N1SDP_NS_SRAM_BASE (0x06000000)
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#define N1SDP_NS_SRAM_SIZE (0x00010000)
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#define N1SDP_MAP_NS_SRAM MAP_REGION_FLAT( \
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N1SDP_NS_SRAM_BASE, \
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N1SDP_NS_SRAM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/* SDS Platform information defines */
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#define N1SDP_SDS_PLATFORM_INFO_STRUCT_ID 8
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#define N1SDP_SDS_PLATFORM_INFO_OFFSET 0
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#define N1SDP_SDS_PLATFORM_INFO_SIZE 4
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#define N1SDP_MAX_DDR_CAPACITY_GB 64
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#define N1SDP_MAX_SECONDARY_COUNT 16
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/* DMC memory command registers */
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#define N1SDP_DMC0_MEMC_CMD_REG 0x4E000008
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#define N1SDP_DMC1_MEMC_CMD_REG 0x4E100008
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/* DMC ERR0CTLR0 registers */
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#define N1SDP_DMC0_ERR0CTLR0_REG 0x4E000708
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#define N1SDP_DMC1_ERR0CTLR0_REG 0x4E100708
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/* Remote DMC memory command registers */
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#define N1SDP_REMOTE_DMC0_MEMC_CMD_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\
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N1SDP_DMC0_MEMC_CMD_REG
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#define N1SDP_REMOTE_DMC1_MEMC_CMD_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\
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N1SDP_DMC1_MEMC_CMD_REG
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/* Remote DMC ERR0CTLR0 registers */
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#define N1SDP_REMOTE_DMC0_ERR0CTLR0_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\
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N1SDP_DMC0_ERR0CTLR0_REG
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#define N1SDP_REMOTE_DMC1_ERR0CTLR0_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\
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N1SDP_DMC1_ERR0CTLR0_REG
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/* DMC memory commands */
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#define N1SDP_DMC_MEMC_CMD_CONFIG 0
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#define N1SDP_DMC_MEMC_CMD_READY 3
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/* DMC ECC enable bit in ERR0CTLR0 register */
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#define N1SDP_DMC_ERR0CTLR0_ECC_EN 0x1
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#endif /* N1SDP_DEF_H */
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