Anson Huang 1552df5d25 Support for NXP's i.MX8 SoCs timer IPC ... NXP's i.MX8 SoCs have system controller (M4 core) which takes control of timer management, including watchdog, srtc and system counter etc., other clusters like Cortex-A35 can send out command via MU (Message Unit) to system controller for timer operation. This patch adds timer IPC(inter-processor communication) support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>		2019-01-17 10:49:48 +08:00
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svc	Support for NXP's i.MX8 SoCs timer IPC	2019-01-17 10:49:48 +08:00
imx8_mu.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
imx8_mu.h	libc: Fix all includes in codebase	2018-08-22 10:26:05 +01:00
ipc.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
sci_api.mk	Support for NXP's i.MX8 SoCs timer IPC	2019-01-17 10:49:48 +08:00