Eleanor Bonnici 45b52c202f Cortex-A57: Implement workaround for erratum 859972 ... Erratum 855972 applies to revision r1p3 or earlier Cortex-A57 CPUs. The recommended workaround is to disable instruction prefetch. Change-Id: I56eeac0b753eb1432bd940083372ad6f7e93b16a Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>		2017-09-07 14:22:02 +01:00
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bl1	FWU: Introduce FWU_SMC_IMAGE_RESET	2017-06-01 14:52:12 +01:00
bl31	include: add U()/ULL() macros for constants	2017-06-14 17:00:30 -07:00
bl32	bl32: add secure interrupt handling in AArch32 sp_min	2017-08-09 15:48:53 +02:00
common	Merge pull request #1078 from douglas-raillard-arm/dr/add_cfi_vector_entry	2017-09-07 00:45:59 +01:00
drivers	Add SMMUv3 driver	2017-08-01 14:33:47 +01:00
lib	Cortex-A57: Implement workaround for erratum 859972	2017-09-07 14:22:02 +01:00
plat	Fix BL2 memory map when OP-TEE is the Secure Payload	2017-09-05 15:03:16 +01:00
services	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
tools_share	Support Trusted OS firmware extra images in TF tools	2017-08-09 18:06:05 +08:00