Eleanor Bonnici 45b52c202f Cortex-A57: Implement workaround for erratum 859972 ... Erratum 855972 applies to revision r1p3 or earlier Cortex-A57 CPUs. The recommended workaround is to disable instruction prefetch. Change-Id: I56eeac0b753eb1432bd940083372ad6f7e93b16a Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>		2017-09-07 14:22:02 +01:00
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aem_generic.S	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
cortex_a35.S	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
cortex_a53.S	CPU: Correct names of implementation-defined aux regs	2017-08-29 13:52:48 +01:00
cortex_a55.S	Fix order of #includes	2017-07-12 14:45:31 +01:00
cortex_a57.S	Cortex-A57: Implement workaround for erratum 859972	2017-09-07 14:22:02 +01:00
cortex_a72.S	CPU: Correct names of implementation-defined aux regs	2017-08-29 13:52:48 +01:00
cortex_a73.S	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
cortex_a75.S	Add support for Cortex-A75 and Cortex-A55 CPUs	2017-06-01 11:44:52 +01:00
cpu_helpers.S	Use a callee-saved register to be AAPCS-compliant	2017-05-24 14:23:08 +01:00
denver.S	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00