170 lines
5.8 KiB
C
170 lines
5.8 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/bl_common.h>
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#include <drivers/arm/gicv3.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <qti_plat.h>
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#include <qtiseclib_defs.h>
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#include <qtiseclib_defs_plat.h>
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/* The GICv3 driver only needs to be initialized in EL3 */
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static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
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/* Array of interrupts to be configured by the gic driver */
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static const interrupt_prop_t qti_interrupt_props[] = {
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INTR_PROP_DESC(QTISECLIB_INT_ID_CPU_WAKEUP_SGI,
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GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(QTISECLIB_INT_ID_RESET_SGI, GIC_HIGHEST_SEC_PRIORITY,
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INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(QTISECLIB_INT_ID_SEC_WDOG_BARK, GIC_HIGHEST_SEC_PRIORITY,
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INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(QTISECLIB_INT_ID_NON_SEC_WDOG_BITE,
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GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
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GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(QTISECLIB_INT_ID_VMIDMT_ERR_CLT_SEC,
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GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(QTISECLIB_INT_ID_VMIDMT_ERR_CLT_NONSEC,
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GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(QTISECLIB_INT_ID_VMIDMT_ERR_CFG_SEC,
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GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(QTISECLIB_INT_ID_VMIDMT_ERR_CFG_NONSEC,
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GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(QTISECLIB_INT_ID_XPU_SEC, GIC_HIGHEST_SEC_PRIORITY,
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INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(QTISECLIB_INT_ID_XPU_NON_SEC, GIC_HIGHEST_SEC_PRIORITY,
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INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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#ifdef QTISECLIB_INT_ID_A1_NOC_ERROR
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INTR_PROP_DESC(QTISECLIB_INT_ID_A1_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
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INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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#endif
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INTR_PROP_DESC(QTISECLIB_INT_ID_A2_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
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INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(QTISECLIB_INT_ID_CONFIG_NOC_ERROR,
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GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(QTISECLIB_INT_ID_DC_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
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INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(QTISECLIB_INT_ID_MEM_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
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INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(QTISECLIB_INT_ID_SYSTEM_NOC_ERROR,
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GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(QTISECLIB_INT_ID_MMSS_NOC_ERROR,
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GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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#ifdef QTISECLIB_INT_ID_LPASS_AGNOC_ERROR
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INTR_PROP_DESC(QTISECLIB_INT_ID_LPASS_AGNOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
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INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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#endif
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#ifdef QTISECLIB_INT_ID_NSP_NOC_ERROR
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INTR_PROP_DESC(QTISECLIB_INT_ID_NSP_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
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INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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#endif
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};
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const gicv3_driver_data_t qti_gic_data = {
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.gicd_base = QTI_GICD_BASE,
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.gicr_base = QTI_GICR_BASE,
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.interrupt_props = qti_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(qti_interrupt_props),
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = rdistif_base_addrs,
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.mpidr_to_core_pos = plat_qti_core_pos_by_mpidr
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};
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void plat_qti_gic_driver_init(void)
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{
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/*
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* The GICv3 driver is initialized in EL3 and does not need
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* to be initialized again in SEL1. This is because the S-EL1
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* can use GIC system registers to manage interrupts and does
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* not need GIC interface base addresses to be configured.
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*/
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gicv3_driver_init(&qti_gic_data);
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}
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/******************************************************************************
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* ARM common helper to initialize the GIC. Only invoked by BL31
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*****************************************************************************/
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void plat_qti_gic_init(void)
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{
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unsigned int i;
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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/* Route secure spi interrupt to ANY. */
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for (i = 0; i < ARRAY_SIZE(qti_interrupt_props); i++) {
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unsigned int int_id = qti_interrupt_props[i].intr_num;
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if (plat_ic_is_spi(int_id)) {
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gicv3_set_spi_routing(int_id, GICV3_IRM_ANY, 0x0);
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}
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}
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}
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void gic_set_spi_routing(unsigned int id, unsigned int irm, u_register_t target)
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{
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gicv3_set_spi_routing(id, irm, target);
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}
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/******************************************************************************
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* ARM common helper to enable the GIC CPU interface
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*****************************************************************************/
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void plat_qti_gic_cpuif_enable(void)
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{
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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/******************************************************************************
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* ARM common helper to disable the GIC CPU interface
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*****************************************************************************/
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void plat_qti_gic_cpuif_disable(void)
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{
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gicv3_cpuif_disable(plat_my_core_pos());
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}
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/******************************************************************************
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* ARM common helper to initialize the per-CPU redistributor interface in GICv3
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*****************************************************************************/
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void plat_qti_gic_pcpu_init(void)
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{
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gicv3_rdistif_init(plat_my_core_pos());
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}
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/******************************************************************************
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* ARM common helpers to power GIC redistributor interface
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*****************************************************************************/
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void plat_qti_gic_redistif_on(void)
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{
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gicv3_rdistif_on(plat_my_core_pos());
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}
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void plat_qti_gic_redistif_off(void)
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{
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gicv3_rdistif_off(plat_my_core_pos());
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}
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