Louis Mayencourt f1be00da0b Use correct type when reading SCR register ... The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>		2020-01-28 11:10:48 +00:00
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aarch32	AArch32: Disable Secure Cycle Counter	2019-09-26 15:36:02 +00:00
aarch64	Use correct type when reading SCR register	2020-01-28 11:10:48 +00:00
cpu_data_array.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00