83 lines
2.0 KiB
C
83 lines
2.0 KiB
C
/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_MT_CIRQ_H
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#define PLAT_MT_CIRQ_H
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#define SYS_CIRQ_BASE U(0x10204000)
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#define CIRQ_IRQ_NUM U(439)
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#define CIRQ_SPI_START U(96)
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/*
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* Define hardware register
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*/
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#define CIRQ_STA_BASE U(0x000)
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#define CIRQ_ACK_BASE U(0x080)
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#define CIRQ_MASK_BASE U(0x100)
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#define CIRQ_MASK_SET_BASE U(0x180)
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#define CIRQ_MASK_CLR_BASE U(0x200)
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#define CIRQ_SENS_BASE U(0x280)
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#define CIRQ_SENS_SET_BASE U(0x300)
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#define CIRQ_SENS_CLR_BASE U(0x380)
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#define CIRQ_POL_BASE U(0x400)
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#define CIRQ_POL_SET_BASE U(0x480)
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#define CIRQ_POL_CLR_BASE U(0x500)
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#define CIRQ_CON U(0x600)
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/*
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* Register placement
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*/
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#define CIRQ_CON_EN_BITS U(0)
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#define CIRQ_CON_EDGE_ONLY_BITS U(1)
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#define CIRQ_CON_FLUSH_BITS U(2)
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#define CIRQ_CON_EVENT_BITS U(31)
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#define CIRQ_CON_SW_RST_BITS U(20)
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#define CIRQ_CON_BITS_MASK U(0x7)
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/*
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* Register setting
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*/
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#define CIRQ_CON_EN U(0x1)
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#define CIRQ_CON_EDGE_ONLY U(0x1)
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#define CIRQ_SW_RESET U(0x1)
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#define CIRQ_CON_FLUSH U(0x1)
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/*
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* Define constant
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*/
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#define CIRQ_CTRL_REG_NUM ((CIRQ_IRQ_NUM + 31U) / 32U)
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#define MT_CIRQ_POL_NEG U(0)
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#define MT_CIRQ_POL_POS U(1)
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#define MT_CIRQ_EDGE_SENSITIVE U(0)
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#define MT_CIRQ_LEVEL_SENSITIVE U(1)
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/*
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* Define macro
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*/
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#define IRQ_TO_CIRQ_NUM(irq) ((irq) - (CIRQ_SPI_START))
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#define CIRQ_TO_IRQ_NUM(cirq) ((cirq) + (CIRQ_SPI_START))
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/*
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* Define cirq events
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*/
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struct cirq_events {
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uint32_t spi_start;
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uint32_t num_of_events;
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uint32_t *wakeup_events;
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};
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/*
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* Define function prototypes.
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*/
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void mt_cirq_enable(void);
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void mt_cirq_disable(void);
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void mt_cirq_clone_gic(void);
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void mt_cirq_flush(void);
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void mt_cirq_sw_reset(void);
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void set_wakeup_sources(uint32_t *list, uint32_t num_of_events);
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void mt_cirq_dump_reg(void);
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#endif /* PLAT_MT_CIRQ_H */
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