195 lines
5.7 KiB
C
195 lines
5.7 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <lib/smccc.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <services/arm_arch_svc.h>
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#include <platform_def.h>
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#include <qti_plat.h>
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#include <qtiseclib_interface.h>
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/*
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* Table of regions for various BL stages to map using the MMU.
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* This doesn't include TZRAM as the 'mem_layout' argument passed to
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* qti_configure_mmu_elx() will give the available subset of that,
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*/
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const mmap_region_t plat_qti_mmap[] = {
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MAP_REGION_FLAT(QTI_DEVICE_BASE, QTI_DEVICE_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(QTI_AOP_CMD_DB_BASE, QTI_AOP_CMD_DB_SIZE,
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MT_NS | MT_RO | MT_EXECUTE_NEVER),
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{0}
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};
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CASSERT(ARRAY_SIZE(plat_qti_mmap) <= MAX_MMAP_REGIONS, assert_max_mmap_regions);
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bool qti_is_overlap_atf_rg(unsigned long long addr, size_t size)
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{
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if (addr > addr + size
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|| (BL31_BASE < addr + size && BL31_LIMIT > addr)) {
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return true;
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}
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return false;
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}
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/*
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* unsigned int plat_qti_my_cluster_pos(void)
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* definition to get the cluster index of the calling CPU.
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* - In ARM v8 (MPIDR_EL1[24]=0)
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* ClusterId = MPIDR_EL1[15:8]
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* - In ARM v8.1 & Later version (MPIDR_EL1[24]=1)
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* ClusterId = MPIDR_EL1[23:15]
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*/
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unsigned int plat_qti_my_cluster_pos(void)
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{
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unsigned int mpidr, cluster_id;
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mpidr = read_mpidr_el1();
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if ((mpidr & MPIDR_MT_MASK) == 0) { /* MT not supported */
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cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
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} else { /* MT supported */
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cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK;
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}
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assert(cluster_id < PLAT_CLUSTER_COUNT);
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return cluster_id;
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}
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/*
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* Set up the page tables for the generic and platform-specific memory regions.
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* The extents of the generic memory regions are specified by the function
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* arguments and consist of:
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* - Trusted SRAM seen by the BL image;
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* - Code section;
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* - Read-only data section;
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* - Coherent memory region, if applicable.
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*/
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void qti_setup_page_tables(uintptr_t total_base,
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size_t total_size,
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uintptr_t code_start,
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uintptr_t code_limit,
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uintptr_t rodata_start,
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uintptr_t rodata_limit,
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uintptr_t coh_start, uintptr_t coh_limit)
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{
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/*
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* Map the Trusted SRAM with appropriate memory attributes.
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* Subsequent mappings will adjust the attributes for specific regions.
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*/
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VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
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(void *)total_base, (void *)(total_base + total_size));
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mmap_add_region(total_base, total_base,
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total_size, MT_MEMORY | MT_RW | MT_SECURE);
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/* Re-map the code section */
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VERBOSE("Code region: %p - %p\n",
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(void *)code_start, (void *)code_limit);
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mmap_add_region(code_start, code_start,
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code_limit - code_start, MT_CODE | MT_SECURE);
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/* Re-map the read-only data section */
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VERBOSE("Read-only data region: %p - %p\n",
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(void *)rodata_start, (void *)rodata_limit);
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mmap_add_region(rodata_start, rodata_start,
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rodata_limit - rodata_start, MT_RO_DATA | MT_SECURE);
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/* Re-map the coherent memory region */
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VERBOSE("Coherent region: %p - %p\n",
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(void *)coh_start, (void *)coh_limit);
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mmap_add_region(coh_start, coh_start,
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coh_limit - coh_start, MT_DEVICE | MT_RW | MT_SECURE);
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/* Now (re-)map the platform-specific memory regions */
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mmap_add(plat_qti_mmap);
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/* Create the page tables to reflect the above mappings */
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init_xlat_tables();
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}
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static inline void qti_align_mem_region(uintptr_t addr, size_t size,
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uintptr_t *aligned_addr,
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size_t *aligned_size)
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{
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*aligned_addr = round_down(addr, PAGE_SIZE);
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*aligned_size = round_up(addr - *aligned_addr + size, PAGE_SIZE);
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}
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int qti_mmap_add_dynamic_region(uintptr_t base_pa, size_t size,
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unsigned int attr)
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{
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uintptr_t aligned_pa;
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size_t aligned_size;
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qti_align_mem_region(base_pa, size, &aligned_pa, &aligned_size);
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if (qti_is_overlap_atf_rg(base_pa, size)) {
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/* Memory shouldn't overlap with TF-A range. */
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return -EPERM;
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}
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return mmap_add_dynamic_region(aligned_pa, aligned_pa, aligned_size,
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attr);
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}
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int qti_mmap_remove_dynamic_region(uintptr_t base_va, size_t size)
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{
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qti_align_mem_region(base_va, size, &base_va, &size);
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return mmap_remove_dynamic_region(base_va, size);
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}
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/*
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* This function returns soc version which mainly consist of below fields
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*
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* soc_version[30:24] = JEP-106 continuation code for the SiP
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* soc_version[23:16] = JEP-106 identification code with parity bit for the SiP
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* soc_version[0:15] = Implementation defined SoC ID
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*/
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int32_t plat_get_soc_version(void)
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{
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uint32_t soc_version = (QTI_SOC_VERSION & QTI_SOC_VERSION_MASK);
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uint32_t jep106az_code = (JEDEC_QTI_BKID << QTI_SOC_CONTINUATION_SHIFT)
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| (JEDEC_QTI_MFID << QTI_SOC_IDENTIFICATION_SHIFT);
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return (int32_t)(jep106az_code | (soc_version));
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}
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/*
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* This function returns soc revision in below format
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*
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* soc_revision[0:30] = SOC revision of specific SOC
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*/
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int32_t plat_get_soc_revision(void)
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{
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return mmio_read_32(QTI_SOC_REVISION_REG) & QTI_SOC_REVISION_MASK;
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}
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/*****************************************************************************
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* plat_smccc_feature_available() - This function checks whether SMCCC feature
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* is availabile for the platform or not.
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* @fid: SMCCC function id
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*
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* Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
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* SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
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*****************************************************************************/
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int32_t plat_smccc_feature_available(u_register_t fid)
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{
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switch (fid) {
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case SMCCC_ARCH_SOC_ID:
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return SMC_ARCH_CALL_SUCCESS;
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default:
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return SMC_ARCH_CALL_NOT_SUPPORTED;
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}
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}
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