211 lines
7.0 KiB
C
211 lines
7.0 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <arm_def.h>
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#include <arm_gic.h>
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#include <assert.h>
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#include <console.h>
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#include <errno.h>
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#include <plat_arm.h>
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#include <platform_def.h>
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#include <psci.h>
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/* Standard ARM platforms are expected to export plat_arm_psci_pm_ops */
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extern const plat_psci_ops_t plat_arm_psci_pm_ops;
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#if ARM_RECOM_STATE_ID_ENC
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extern unsigned int arm_pm_idle_states[];
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#endif /* __ARM_RECOM_STATE_ID_ENC__ */
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#if !ARM_RECOM_STATE_ID_ENC
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/*******************************************************************************
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* ARM standard platform handler called to check the validity of the power state
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* parameter.
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******************************************************************************/
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int arm_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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int pstate = psci_get_pstate_type(power_state);
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int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
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int i;
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assert(req_state);
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if (pwr_lvl > PLAT_MAX_PWR_LVL)
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return PSCI_E_INVALID_PARAMS;
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/* Sanity check the requested state */
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if (pstate == PSTATE_TYPE_STANDBY) {
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/*
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* It's possible to enter standby only on power level 0
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* Ignore any other power level.
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*/
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if (pwr_lvl != ARM_PWR_LVL0)
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return PSCI_E_INVALID_PARAMS;
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req_state->pwr_domain_state[ARM_PWR_LVL0] =
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ARM_LOCAL_STATE_RET;
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} else {
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for (i = ARM_PWR_LVL0; i <= pwr_lvl; i++)
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req_state->pwr_domain_state[i] =
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ARM_LOCAL_STATE_OFF;
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}
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/*
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* We expect the 'state id' to be zero.
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*/
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if (psci_get_pstate_id(power_state))
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return PSCI_E_INVALID_PARAMS;
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return PSCI_E_SUCCESS;
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}
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#else
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/*******************************************************************************
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* ARM standard platform handler called to check the validity of the power
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* state parameter. The power state parameter has to be a composite power
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* state.
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******************************************************************************/
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int arm_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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unsigned int state_id;
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int i;
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assert(req_state);
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/*
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* Currently we are using a linear search for finding the matching
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* entry in the idle power state array. This can be made a binary
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* search if the number of entries justify the additional complexity.
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*/
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for (i = 0; !!arm_pm_idle_states[i]; i++) {
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if (power_state == arm_pm_idle_states[i])
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break;
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}
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/* Return error if entry not found in the idle state array */
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if (!arm_pm_idle_states[i])
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return PSCI_E_INVALID_PARAMS;
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i = 0;
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state_id = psci_get_pstate_id(power_state);
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/* Parse the State ID and populate the state info parameter */
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while (state_id) {
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req_state->pwr_domain_state[i++] = state_id &
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ARM_LOCAL_PSTATE_MASK;
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state_id >>= ARM_LOCAL_PSTATE_WIDTH;
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}
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return PSCI_E_SUCCESS;
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}
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#endif /* __ARM_RECOM_STATE_ID_ENC__ */
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/*******************************************************************************
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* ARM standard platform handler called to check the validity of the non secure
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* entrypoint.
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******************************************************************************/
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int arm_validate_ns_entrypoint(uintptr_t entrypoint)
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{
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/*
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* Check if the non secure entrypoint lies within the non
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* secure DRAM.
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*/
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if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint <
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(ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE)))
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return PSCI_E_SUCCESS;
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if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint <
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(ARM_DRAM2_BASE + ARM_DRAM2_SIZE)))
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return PSCI_E_SUCCESS;
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return PSCI_E_INVALID_ADDRESS;
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}
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/******************************************************************************
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* Helper function to resume the platform from system suspend. Reinitialize
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* the system components which are not in the Always ON power domain.
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* TODO: Unify the platform setup when waking up from cold boot and system
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* resume in arm_bl31_platform_setup().
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*****************************************************************************/
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void arm_system_pwr_domain_resume(void)
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{
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console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
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ARM_CONSOLE_BAUDRATE);
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/* Assert system power domain is available on the platform */
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assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2);
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arm_gic_setup();
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plat_arm_security_setup();
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arm_configure_sys_timer();
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}
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/*******************************************************************************
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* Private function to program the mailbox for a cpu before it is released
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* from reset. This function assumes that the Trusted mail box base is within
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* the ARM_SHARED_RAM region
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******************************************************************************/
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void arm_program_trusted_mailbox(uintptr_t address)
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{
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uintptr_t *mailbox = (void *) PLAT_ARM_TRUSTED_MAILBOX_BASE;
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*mailbox = address;
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/*
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* Ensure that the PLAT_ARM_TRUSTED_MAILBOX_BASE is within
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* ARM_SHARED_RAM region.
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*/
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assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) &&
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((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= \
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(ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE)));
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/* Flush data cache if the mail box shared RAM is cached */
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#if PLAT_ARM_SHARED_RAM_CACHED
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flush_dcache_range((uintptr_t) mailbox, sizeof(*mailbox));
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#endif
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}
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/*******************************************************************************
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* The ARM Standard platform definition of platform porting API
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* `plat_setup_psci_ops`.
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******************************************************************************/
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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*psci_ops = &plat_arm_psci_pm_ops;
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/* Setup mailbox with entry point. */
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arm_program_trusted_mailbox(sec_entrypoint);
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return 0;
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}
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