300 lines
8.4 KiB
C
300 lines
8.4 KiB
C
/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <inttypes.h>
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#include <stdint.h>
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#include <common/debug.h>
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#include <common/fdt_wrappers.h>
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#include <fconf_hw_config_getter.h>
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#include <libfdt.h>
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#include <plat/common/platform.h>
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struct gicv3_config_t gicv3_config;
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struct hw_topology_t soc_topology;
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struct uart_serial_config_t uart_serial_config;
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struct cpu_timer_t cpu_timer;
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#define ILLEGAL_ADDR ULL(~0)
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int fconf_populate_gicv3_config(uintptr_t config)
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{
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int err;
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int node;
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uintptr_t addr;
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/* Necessary to work with libfdt APIs */
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const void *hw_config_dtb = (const void *)config;
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/*
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* Find the offset of the node containing "arm,gic-v3" compatible property.
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* Populating fconf strucutures dynamically is not supported for legacy
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* systems which use GICv2 IP. Simply skip extracting GIC properties.
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*/
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node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,gic-v3");
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if (node < 0) {
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WARN("FCONF: Unable to locate node with arm,gic-v3 compatible property\n");
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return 0;
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}
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/* The GICv3 DT binding holds at least two address/size pairs,
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* the first describing the distributor, the second the redistributors.
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* See: bindings/interrupt-controller/arm,gic-v3.yaml
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*/
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err = fdt_get_reg_props_by_index(hw_config_dtb, node, 0, &addr, NULL);
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if (err < 0) {
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ERROR("FCONF: Failed to read GICD reg property of GIC node\n");
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return err;
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}
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gicv3_config.gicd_base = addr;
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err = fdt_get_reg_props_by_index(hw_config_dtb, node, 1, &addr, NULL);
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if (err < 0) {
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ERROR("FCONF: Failed to read GICR reg property of GIC node\n");
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} else {
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gicv3_config.gicr_base = addr;
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}
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return err;
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}
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int fconf_populate_topology(uintptr_t config)
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{
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int err, node, cluster_node, core_node, thread_node;
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uint32_t cluster_count = 0, max_cpu_per_cluster = 0, total_cpu_count = 0;
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uint32_t max_pwr_lvl = 0;
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/* Necessary to work with libfdt APIs */
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const void *hw_config_dtb = (const void *)config;
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/* Find the offset of the node containing "arm,psci-1.0" compatible property */
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node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,psci-1.0");
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if (node < 0) {
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ERROR("FCONF: Unable to locate node with arm,psci-1.0 compatible property\n");
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return node;
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}
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err = fdt_read_uint32(hw_config_dtb, node, "max-pwr-lvl", &max_pwr_lvl);
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if (err < 0) {
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/*
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* Some legacy FVP dts may not have this property. Assign the default
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* value.
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*/
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WARN("FCONF: Could not locate max-pwr-lvl property\n");
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max_pwr_lvl = 2;
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}
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assert(max_pwr_lvl <= MPIDR_AFFLVL2);
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/* Find the offset of the "cpus" node */
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node = fdt_path_offset(hw_config_dtb, "/cpus");
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if (node < 0) {
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ERROR("FCONF: Node '%s' not found in hardware configuration dtb\n", "cpus");
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return node;
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}
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/* A typical cpu-map node in a device tree is shown here for reference
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU2>;
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};
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core1 {
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cpu = <&CPU3>;
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};
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};
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};
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*/
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/* Locate the cpu-map child node */
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node = fdt_subnode_offset(hw_config_dtb, node, "cpu-map");
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if (node < 0) {
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ERROR("FCONF: Node '%s' not found in hardware configuration dtb\n", "cpu-map");
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return node;
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}
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uint32_t cpus_per_cluster[PLAT_ARM_CLUSTER_COUNT] = {0};
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/* Iterate through cluster nodes */
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fdt_for_each_subnode(cluster_node, hw_config_dtb, node) {
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assert(cluster_count < PLAT_ARM_CLUSTER_COUNT);
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/* Iterate through core nodes */
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fdt_for_each_subnode(core_node, hw_config_dtb, cluster_node) {
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/* core nodes may have child nodes i.e., "thread" nodes */
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if (fdt_first_subnode(hw_config_dtb, core_node) < 0) {
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cpus_per_cluster[cluster_count]++;
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} else {
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/* Multi-threaded CPU description is found in dtb */
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fdt_for_each_subnode(thread_node, hw_config_dtb, core_node) {
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cpus_per_cluster[cluster_count]++;
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}
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/* Since in some dtbs, core nodes may not have thread node,
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* no need to error if even one child node is not found.
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*/
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}
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}
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/* Ensure every cluster node has at least 1 child node */
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if (cpus_per_cluster[cluster_count] < 1U) {
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ERROR("FCONF: Unable to locate the core node in cluster %d\n", cluster_count);
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return -1;
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}
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VERBOSE("CLUSTER ID: %d cpu-count: %d\n", cluster_count,
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cpus_per_cluster[cluster_count]);
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/* Find the maximum number of cpus in any cluster */
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max_cpu_per_cluster = MAX(max_cpu_per_cluster, cpus_per_cluster[cluster_count]);
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total_cpu_count += cpus_per_cluster[cluster_count];
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cluster_count++;
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}
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/* At least one cluster node is expected in hardware configuration dtb */
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if (cluster_count < 1U) {
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ERROR("FCONF: Unable to locate the cluster node in cpu-map node\n");
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return -1;
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}
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soc_topology.plat_max_pwr_level = max_pwr_lvl;
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soc_topology.plat_cluster_count = cluster_count;
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soc_topology.cluster_cpu_count = max_cpu_per_cluster;
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soc_topology.plat_cpu_count = total_cpu_count;
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return 0;
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}
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int fconf_populate_uart_config(uintptr_t config)
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{
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int uart_node, node, err;
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uintptr_t addr;
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const char *path;
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uint32_t phandle;
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uint64_t translated_addr;
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/* Necessary to work with libfdt APIs */
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const void *hw_config_dtb = (const void *)config;
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/*
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* uart child node is indirectly referenced through its path which is
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* specified in the `serial1` property of the "aliases" node.
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* Note that TF-A boot console is mapped to serial0 while runtime
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* console is mapped to serial1.
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*/
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path = fdt_get_alias(hw_config_dtb, "serial1");
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if (path == NULL) {
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ERROR("FCONF: Could not read serial1 property in aliases node\n");
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return -1;
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}
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/* Find the offset of the uart serial node */
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uart_node = fdt_path_offset(hw_config_dtb, path);
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if (uart_node < 0) {
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ERROR("FCONF: Failed to locate uart serial node using its path\n");
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return -1;
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}
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/* uart serial node has its offset and size of address in reg property */
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err = fdt_get_reg_props_by_index(hw_config_dtb, uart_node, 0, &addr,
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NULL);
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if (err < 0) {
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ERROR("FCONF: Failed to read reg property of '%s' node\n",
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"uart serial");
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return err;
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}
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VERBOSE("FCONF: UART node address: %lx\n", addr);
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/*
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* Perform address translation of local device address to CPU address
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* domain.
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*/
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translated_addr = fdtw_translate_address(hw_config_dtb,
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uart_node, (uint64_t)addr);
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if (translated_addr == ILLEGAL_ADDR) {
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ERROR("FCONF: failed to translate UART node base address");
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return -1;
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}
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uart_serial_config.uart_base = translated_addr;
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VERBOSE("FCONF: UART serial device base address: %" PRIx64 "\n",
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uart_serial_config.uart_base);
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/*
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* The phandle of the DT node which captures the clock info of uart
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* serial node is specified in the "clocks" property.
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*/
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err = fdt_read_uint32(hw_config_dtb, uart_node, "clocks", &phandle);
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if (err < 0) {
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ERROR("FCONF: Could not read clocks property in uart serial node\n");
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return err;
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}
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node = fdt_node_offset_by_phandle(hw_config_dtb, phandle);
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if (node < 0) {
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ERROR("FCONF: Failed to locate clk node using its path\n");
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return node;
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}
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/*
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* Retrieve clock frequency. We assume clock provider generates a fixed
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* clock.
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*/
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err = fdt_read_uint32(hw_config_dtb, node, "clock-frequency",
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&uart_serial_config.uart_clk);
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if (err < 0) {
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ERROR("FCONF: Could not read clock-frequency property in clk node\n");
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return err;
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}
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VERBOSE("FCONF: UART serial device clk frequency: %x\n",
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uart_serial_config.uart_clk);
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return 0;
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}
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int fconf_populate_cpu_timer(uintptr_t config)
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{
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int err, node;
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/* Necessary to work with libfdt APIs */
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const void *hw_config_dtb = (const void *)config;
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/* Find the node offset point to "arm,armv8-timer" compatible property,
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* a per-core architected timer attached to a GIC to deliver its per-processor
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* interrupts via PPIs */
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node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,armv8-timer");
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if (node < 0) {
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ERROR("FCONF: Unrecognized hardware configuration dtb (%d)\n", node);
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return node;
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}
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/* Locate the cell holding the clock-frequency, an optional field */
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err = fdt_read_uint32(hw_config_dtb, node, "clock-frequency", &cpu_timer.clock_freq);
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if (err < 0) {
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WARN("FCONF failed to read clock-frequency property\n");
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}
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return 0;
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}
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FCONF_REGISTER_POPULATOR(HW_CONFIG, gicv3_config, fconf_populate_gicv3_config);
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FCONF_REGISTER_POPULATOR(HW_CONFIG, topology, fconf_populate_topology);
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FCONF_REGISTER_POPULATOR(HW_CONFIG, uart_config, fconf_populate_uart_config);
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FCONF_REGISTER_POPULATOR(HW_CONFIG, cpu_timer, fconf_populate_cpu_timer);
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