477 lines
13 KiB
C
477 lines
13 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <inttypes.h>
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#include <stdint.h>
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#include <string.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <context.h>
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#include <denver.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/mmio.h>
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#include <mce.h>
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#include <mce_private.h>
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#include <t18x_ari.h>
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#include <tegra_def.h>
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#include <tegra_platform.h>
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/* NVG functions handlers */
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static arch_mce_ops_t nvg_mce_ops = {
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.enter_cstate = nvg_enter_cstate,
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.update_cstate_info = nvg_update_cstate_info,
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.update_crossover_time = nvg_update_crossover_time,
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.read_cstate_stats = nvg_read_cstate_stats,
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.write_cstate_stats = nvg_write_cstate_stats,
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.call_enum_misc = ari_enumeration_misc,
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.is_ccx_allowed = nvg_is_ccx_allowed,
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.is_sc7_allowed = nvg_is_sc7_allowed,
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.online_core = nvg_online_core,
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.cc3_ctrl = nvg_cc3_ctrl,
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.update_reset_vector = ari_reset_vector_update,
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.roc_flush_cache = ari_roc_flush_cache,
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.roc_flush_cache_trbits = ari_roc_flush_cache_trbits,
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.roc_clean_cache = ari_roc_clean_cache,
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.read_write_mca = ari_read_write_mca,
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.update_ccplex_gsc = ari_update_ccplex_gsc,
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.enter_ccplex_state = ari_enter_ccplex_state,
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.read_write_uncore_perfmon = ari_read_write_uncore_perfmon,
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.misc_ccplex = ari_misc_ccplex
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};
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/* ARI functions handlers */
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static arch_mce_ops_t ari_mce_ops = {
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.enter_cstate = ari_enter_cstate,
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.update_cstate_info = ari_update_cstate_info,
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.update_crossover_time = ari_update_crossover_time,
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.read_cstate_stats = ari_read_cstate_stats,
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.write_cstate_stats = ari_write_cstate_stats,
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.call_enum_misc = ari_enumeration_misc,
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.is_ccx_allowed = ari_is_ccx_allowed,
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.is_sc7_allowed = ari_is_sc7_allowed,
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.online_core = ari_online_core,
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.cc3_ctrl = ari_cc3_ctrl,
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.update_reset_vector = ari_reset_vector_update,
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.roc_flush_cache = ari_roc_flush_cache,
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.roc_flush_cache_trbits = ari_roc_flush_cache_trbits,
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.roc_clean_cache = ari_roc_clean_cache,
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.read_write_mca = ari_read_write_mca,
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.update_ccplex_gsc = ari_update_ccplex_gsc,
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.enter_ccplex_state = ari_enter_ccplex_state,
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.read_write_uncore_perfmon = ari_read_write_uncore_perfmon,
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.misc_ccplex = ari_misc_ccplex
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};
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typedef struct {
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uint32_t ari_base;
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arch_mce_ops_t *ops;
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} mce_config_t;
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/* Table to hold the per-CPU ARI base address and function handlers */
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static mce_config_t mce_cfg_table[MCE_ARI_APERTURES_MAX] = {
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{
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/* A57 Core 0 */
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.ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_0_OFFSET,
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.ops = &ari_mce_ops,
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},
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{
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/* A57 Core 1 */
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.ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_1_OFFSET,
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.ops = &ari_mce_ops,
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},
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{
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/* A57 Core 2 */
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.ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_2_OFFSET,
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.ops = &ari_mce_ops,
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},
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{
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/* A57 Core 3 */
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.ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_3_OFFSET,
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.ops = &ari_mce_ops,
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},
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{
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/* D15 Core 0 */
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.ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_4_OFFSET,
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.ops = &nvg_mce_ops,
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},
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{
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/* D15 Core 1 */
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.ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_5_OFFSET,
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.ops = &nvg_mce_ops,
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}
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};
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static uint32_t mce_get_curr_cpu_ari_base(void)
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{
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uint64_t mpidr = read_mpidr();
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uint64_t cpuid = mpidr & MPIDR_CPU_MASK;
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uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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/*
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* T186 has 2 CPU clusters, one with Denver CPUs and the other with
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* ARM CortexA-57 CPUs. Each cluster consists of 4 CPUs and the CPU
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* numbers start from 0. In order to get the proper arch_mce_ops_t
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* struct, we have to convert the Denver CPU ids to the corresponding
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* indices in the mce_ops_table array.
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*/
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if (impl == DENVER_IMPL) {
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cpuid |= 0x4U;
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}
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return mce_cfg_table[cpuid].ari_base;
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}
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static arch_mce_ops_t *mce_get_curr_cpu_ops(void)
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{
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uint64_t mpidr = read_mpidr();
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uint64_t cpuid = mpidr & MPIDR_CPU_MASK;
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uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) &
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MIDR_IMPL_MASK;
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/*
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* T186 has 2 CPU clusters, one with Denver CPUs and the other with
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* ARM CortexA-57 CPUs. Each cluster consists of 4 CPUs and the CPU
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* numbers start from 0. In order to get the proper arch_mce_ops_t
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* struct, we have to convert the Denver CPU ids to the corresponding
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* indices in the mce_ops_table array.
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*/
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if (impl == DENVER_IMPL) {
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cpuid |= 0x4U;
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}
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return mce_cfg_table[cpuid].ops;
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}
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/*******************************************************************************
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* Common handler for all MCE commands
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******************************************************************************/
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int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
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uint64_t arg2)
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{
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const arch_mce_ops_t *ops;
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gp_regs_t *gp_regs = get_gpregs_ctx(cm_get_context(NON_SECURE));
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uint32_t cpu_ari_base;
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uint64_t ret64 = 0, arg3, arg4, arg5;
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int32_t ret = 0;
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assert(gp_regs != NULL);
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/* get a pointer to the CPU's arch_mce_ops_t struct */
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ops = mce_get_curr_cpu_ops();
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/* get the CPU's ARI base address */
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cpu_ari_base = mce_get_curr_cpu_ari_base();
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switch (cmd) {
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case (uint64_t)MCE_CMD_ENTER_CSTATE:
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ret = ops->enter_cstate(cpu_ari_base, arg0, arg1);
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break;
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case (uint64_t)MCE_CMD_UPDATE_CSTATE_INFO:
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/*
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* get the parameters required for the update cstate info
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* command
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*/
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arg3 = read_ctx_reg(gp_regs, CTX_GPREG_X4);
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arg4 = read_ctx_reg(gp_regs, CTX_GPREG_X5);
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arg5 = read_ctx_reg(gp_regs, CTX_GPREG_X6);
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ret = ops->update_cstate_info(cpu_ari_base, (uint32_t)arg0,
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(uint32_t)arg1, (uint32_t)arg2, (uint8_t)arg3,
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(uint32_t)arg4, (uint8_t)arg5);
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write_ctx_reg(gp_regs, CTX_GPREG_X4, (0ULL));
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write_ctx_reg(gp_regs, CTX_GPREG_X5, (0ULL));
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write_ctx_reg(gp_regs, CTX_GPREG_X6, (0ULL));
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break;
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case (uint64_t)MCE_CMD_UPDATE_CROSSOVER_TIME:
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ret = ops->update_crossover_time(cpu_ari_base, arg0, arg1);
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break;
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case (uint64_t)MCE_CMD_READ_CSTATE_STATS:
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ret64 = ops->read_cstate_stats(cpu_ari_base, arg0);
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/* update context to return cstate stats value */
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write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64));
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write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64));
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break;
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case (uint64_t)MCE_CMD_WRITE_CSTATE_STATS:
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ret = ops->write_cstate_stats(cpu_ari_base, arg0, arg1);
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break;
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case (uint64_t)MCE_CMD_IS_CCX_ALLOWED:
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ret = ops->is_ccx_allowed(cpu_ari_base, arg0, arg1);
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/* update context to return CCx status value */
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write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint64_t)(ret));
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break;
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case (uint64_t)MCE_CMD_IS_SC7_ALLOWED:
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ret = ops->is_sc7_allowed(cpu_ari_base, arg0, arg1);
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/* update context to return SC7 status value */
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write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint64_t)(ret));
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write_ctx_reg(gp_regs, CTX_GPREG_X3, (uint64_t)(ret));
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break;
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case (uint64_t)MCE_CMD_ONLINE_CORE:
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ret = ops->online_core(cpu_ari_base, arg0);
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break;
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case (uint64_t)MCE_CMD_CC3_CTRL:
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ret = ops->cc3_ctrl(cpu_ari_base, arg0, arg1, arg2);
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break;
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case (uint64_t)MCE_CMD_ECHO_DATA:
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ret64 = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_ECHO,
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arg0);
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/* update context to return if echo'd data matched source */
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write_ctx_reg(gp_regs, CTX_GPREG_X1, ((ret64 == arg0) ?
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1ULL : 0ULL));
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write_ctx_reg(gp_regs, CTX_GPREG_X2, ((ret64 == arg0) ?
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1ULL : 0ULL));
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break;
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case (uint64_t)MCE_CMD_READ_VERSIONS:
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ret64 = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_VERSION,
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arg0);
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/*
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* version = minor(63:32) | major(31:0). Update context
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* to return major and minor version number.
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*/
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write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64));
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write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64 >> 32ULL));
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break;
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case (uint64_t)MCE_CMD_ENUM_FEATURES:
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ret64 = ops->call_enum_misc(cpu_ari_base,
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TEGRA_ARI_MISC_FEATURE_LEAF_0, arg0);
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/* update context to return features value */
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write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64));
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break;
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case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
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ret = ops->roc_flush_cache_trbits(cpu_ari_base);
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break;
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case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE:
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ret = ops->roc_flush_cache(cpu_ari_base);
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break;
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case (uint64_t)MCE_CMD_ROC_CLEAN_CACHE:
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ret = ops->roc_clean_cache(cpu_ari_base);
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break;
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case (uint64_t)MCE_CMD_ENUM_READ_MCA:
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ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1);
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/* update context to return MCA data/error */
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write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64));
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write_ctx_reg(gp_regs, CTX_GPREG_X2, (arg1));
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write_ctx_reg(gp_regs, CTX_GPREG_X3, (ret64));
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break;
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case (uint64_t)MCE_CMD_ENUM_WRITE_MCA:
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ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1);
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/* update context to return MCA error */
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write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64));
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write_ctx_reg(gp_regs, CTX_GPREG_X3, (ret64));
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break;
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#if ENABLE_CHIP_VERIFICATION_HARNESS
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case (uint64_t)MCE_CMD_ENABLE_LATIC:
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/*
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* This call is not for production use. The constant value,
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* 0xFFFF0000, is specific to allowing for enabling LATIC on
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* pre-production parts for the chip verification harness.
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*
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* Enabling LATIC allows S/W to read the MINI ISPs in the
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* CCPLEX. The ISMs are used for various measurements relevant
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* to particular locations in the Silicon. They are small
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* counters which can be polled to determine how fast a
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* particular location in the Silicon is.
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*/
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ops->enter_ccplex_state(mce_get_curr_cpu_ari_base(),
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0xFFFF0000);
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break;
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#endif
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case (uint64_t)MCE_CMD_UNCORE_PERFMON_REQ:
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ret = ops->read_write_uncore_perfmon(cpu_ari_base, arg0, &arg1);
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/* update context to return data */
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write_ctx_reg(gp_regs, CTX_GPREG_X1, (arg1));
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break;
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case (uint64_t)MCE_CMD_MISC_CCPLEX:
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ops->misc_ccplex(cpu_ari_base, arg0, arg1);
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break;
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default:
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ERROR("unknown MCE command (%" PRIu64 ")\n", cmd);
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ret = EINVAL;
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break;
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}
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return ret;
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}
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/*******************************************************************************
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* Handler to update the reset vector for CPUs
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******************************************************************************/
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int32_t mce_update_reset_vector(void)
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{
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const arch_mce_ops_t *ops = mce_get_curr_cpu_ops();
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ops->update_reset_vector(mce_get_curr_cpu_ari_base());
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return 0;
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}
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static int32_t mce_update_ccplex_gsc(tegra_ari_gsc_index_t gsc_idx)
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{
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const arch_mce_ops_t *ops = mce_get_curr_cpu_ops();
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ops->update_ccplex_gsc(mce_get_curr_cpu_ari_base(), gsc_idx);
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return 0;
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}
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/*******************************************************************************
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* Handler to update carveout values for Video Memory Carveout region
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******************************************************************************/
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int32_t mce_update_gsc_videomem(void)
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{
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return mce_update_ccplex_gsc(TEGRA_ARI_GSC_VPR_IDX);
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}
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/*******************************************************************************
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* Handler to update carveout values for TZDRAM aperture
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******************************************************************************/
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int32_t mce_update_gsc_tzdram(void)
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{
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return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZ_DRAM_IDX);
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}
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/*******************************************************************************
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* Handler to shutdown/reset the entire system
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******************************************************************************/
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__dead2 void mce_enter_ccplex_state(uint32_t state_idx)
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{
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const arch_mce_ops_t *ops = mce_get_curr_cpu_ops();
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/* sanity check state value */
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if ((state_idx != TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) &&
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(state_idx != TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT)) {
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panic();
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}
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ops->enter_ccplex_state(mce_get_curr_cpu_ari_base(), state_idx);
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/* wait till the CCPLEX powers down */
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for (;;) {
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;
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}
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}
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/*******************************************************************************
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* Handler to issue the UPDATE_CSTATE_INFO request
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******************************************************************************/
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void mce_update_cstate_info(const mce_cstate_info_t *cstate)
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{
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const arch_mce_ops_t *ops = mce_get_curr_cpu_ops();
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/* issue the UPDATE_CSTATE_INFO request */
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ops->update_cstate_info(mce_get_curr_cpu_ari_base(), cstate->cluster,
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cstate->ccplex, cstate->system, cstate->system_state_force,
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cstate->wake_mask, cstate->update_wake_mask);
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}
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/*******************************************************************************
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* Handler to read the MCE firmware version and check if it is compatible
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* with interface header the BL3-1 was compiled against
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******************************************************************************/
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void mce_verify_firmware_version(void)
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{
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const arch_mce_ops_t *ops;
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uint32_t cpu_ari_base;
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uint64_t version;
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uint32_t major, minor;
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/*
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* MCE firmware is not supported on simulation platforms.
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*/
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if (tegra_platform_is_emulation()) {
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INFO("MCE firmware is not supported\n");
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} else {
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/* get a pointer to the CPU's arch_mce_ops_t struct */
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ops = mce_get_curr_cpu_ops();
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/* get the CPU's ARI base address */
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cpu_ari_base = mce_get_curr_cpu_ari_base();
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/*
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* Read the MCE firmware version and extract the major and minor
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* version fields
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*/
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version = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_VERSION, 0);
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major = (uint32_t)version;
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minor = (uint32_t)(version >> 32);
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INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor,
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TEGRA_ARI_VERSION_MAJOR, TEGRA_ARI_VERSION_MINOR);
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/*
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* Verify that the MCE firmware version and the interface header
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* match
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*/
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if (major != TEGRA_ARI_VERSION_MAJOR) {
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ERROR("ARI major version mismatch\n");
|
|
panic();
|
|
}
|
|
|
|
if (minor < TEGRA_ARI_VERSION_MINOR) {
|
|
ERROR("ARI minor version mismatch\n");
|
|
panic();
|
|
}
|
|
}
|
|
}
|