98 lines
2.7 KiB
C
98 lines
2.7 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <inttypes.h>
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#include <stdint.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <errno.h>
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include <memctrl.h>
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#include <pmc.h>
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#include <tegra_private.h>
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#include <tegra_platform.h>
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#include <tegra_def.h>
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/*******************************************************************************
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* PMC parameters
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******************************************************************************/
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#define PMC_READ U(0xaa)
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#define PMC_WRITE U(0xbb)
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/*******************************************************************************
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* Tegra210 SiP SMCs
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******************************************************************************/
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#define TEGRA_SIP_PMC_COMMANDS U(0xC2FFFE00)
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/*******************************************************************************
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* This function is responsible for handling all T210 SiP calls
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******************************************************************************/
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int plat_sip_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x2,
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uint64_t x3,
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uint64_t x4,
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const void *cookie,
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void *handle,
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uint64_t flags)
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{
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uint32_t val, ns;
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/* Determine which security state this SMC originated from */
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ns = is_caller_non_secure(flags);
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if (!ns)
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SMC_RET1(handle, SMC_UNK);
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if (smc_fid == TEGRA_SIP_PMC_COMMANDS) {
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/* check the address is within PMC range and is 4byte aligned */
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if ((x2 >= TEGRA_PMC_SIZE) || (x2 & 0x3))
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return -EINVAL;
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switch (x2) {
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/* Black listed PMC registers */
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case PMC_SCRATCH1:
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case PMC_SCRATCH31 ... PMC_SCRATCH33:
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case PMC_SCRATCH40:
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case PMC_SCRATCH42:
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case PMC_SCRATCH43 ... PMC_SCRATCH48:
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case PMC_SCRATCH50 ... PMC_SCRATCH51:
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case PMC_SCRATCH56 ... PMC_SCRATCH57:
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/* PMC secure-only registers are not accessible */
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case PMC_DPD_ENABLE_0:
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case PMC_FUSE_CONTROL_0:
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case PMC_CRYPTO_OP_0:
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case PMC_TSC_MULT_0:
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case PMC_STICKY_BIT:
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ERROR("%s: error offset=0x%" PRIx64 "\n", __func__, x2);
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return -EFAULT;
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default:
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/* Valid register */
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break;
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}
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/* Perform PMC read/write */
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if (x1 == PMC_READ) {
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val = mmio_read_32((uint32_t)(TEGRA_PMC_BASE + x2));
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, val);
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} else if (x1 == PMC_WRITE) {
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mmio_write_32((uint32_t)(TEGRA_PMC_BASE + x2), (uint32_t)x3);
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} else {
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return -EINVAL;
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}
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} else {
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return -ENOTSUP;
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}
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return 0;
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}
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