213 lines
5.7 KiB
C
213 lines
5.7 KiB
C
/*
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* Copyright 2018-2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <assert.h>
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#include <inttypes.h>
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#include <stdint.h>
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#ifdef LS_EL3_INTERRUPT_HANDLER
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#include <ls_interrupt_mgmt.h>
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#endif
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#include <mmu_def.h>
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#include <plat_common.h>
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/*
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* Placeholder variables for copying the arguments that have been passed to
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* BL31 from BL2.
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*/
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#ifdef TEST_BL31
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#define SPSR_FOR_EL2H 0x3C9
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#define SPSR_FOR_EL1H 0x3C5
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#else
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static entry_point_info_t bl31_image_ep_info;
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#endif
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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static dram_regions_info_t dram_regions_info = {0};
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static uint64_t rcw_porsr1;
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/* Return the pointer to the 'dram_regions_info structure of the DRAM.
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* This structure is populated after init_ddr().
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*/
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dram_regions_info_t *get_dram_regions_info(void)
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{
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return &dram_regions_info;
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}
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/* Return the RCW.PORSR1 value which was passed in from BL2
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*/
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uint64_t bl31_get_porsr1(void)
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{
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return rcw_porsr1;
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}
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/*
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* Return pointer to the 'entry_point_info' structure of the next image for the
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* security state specified:
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* - BL33 corresponds to the non-secure image type; while
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* - BL32 corresponds to the secure image type.
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* - A NULL pointer is returned, if the image does not exist.
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*/
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *next_image_info;
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assert(sec_state_is_valid(type));
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next_image_info = (type == NON_SECURE)
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? &bl33_image_ep_info : &bl32_image_ep_info;
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#ifdef TEST_BL31
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next_image_info->pc = _get_test_entry();
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next_image_info->spsr = SPSR_FOR_EL2H;
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next_image_info->h.attr = NON_SECURE;
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#endif
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if (next_image_info->pc != 0U) {
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return next_image_info;
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} else {
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return NULL;
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}
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}
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/*
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* Perform any BL31 early platform setup common to NXP platforms.
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* - Here is an opportunity to copy parameters passed by the calling EL (S-EL1
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* in BL2 & S-EL3 in BL1) before they are lost (potentially).
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* - This needs to be done before the MMU is initialized so that the
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* memory layout can be used while creating page tables.
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* - BL2 has flushed this information to memory, in order to fetch latest data.
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*/
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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#ifndef TEST_BL31
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int i = 0;
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void *from_bl2 = (void *)arg0;
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#endif
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soc_early_platform_setup2();
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#ifdef TEST_BL31
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dram_regions_info.num_dram_regions = 2;
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dram_regions_info.total_dram_size = 0x100000000;
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dram_regions_info.region[0].addr = 0x80000000;
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dram_regions_info.region[0].size = 0x80000000;
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dram_regions_info.region[1].addr = 0x880000000;
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dram_regions_info.region[1].size = 0x80000000;
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bl33_image_ep_info.pc = _get_test_entry();
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#else
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/*
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* Check params passed from BL2 should not be NULL,
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*/
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bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
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assert(params_from_bl2 != NULL);
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assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
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assert(params_from_bl2->h.version >= VERSION_2);
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bl_params_node_t *bl_params = params_from_bl2->head;
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/*
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* Copy BL33 and BL32 (if present), entry point information.
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* They are stored in Secure RAM, in BL2's address space.
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*/
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while (bl_params != NULL) {
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if (bl_params->image_id == BL31_IMAGE_ID) {
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bl31_image_ep_info = *bl_params->ep_info;
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dram_regions_info_t *loc_dram_regions_info =
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(dram_regions_info_t *) bl31_image_ep_info.args.arg3;
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dram_regions_info.num_dram_regions =
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loc_dram_regions_info->num_dram_regions;
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dram_regions_info.total_dram_size =
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loc_dram_regions_info->total_dram_size;
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VERBOSE("Number of DRAM Regions = %" PRIx64 "\n",
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dram_regions_info.num_dram_regions);
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for (i = 0; i < dram_regions_info.num_dram_regions;
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i++) {
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dram_regions_info.region[i].addr =
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loc_dram_regions_info->region[i].addr;
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dram_regions_info.region[i].size =
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loc_dram_regions_info->region[i].size;
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VERBOSE("DRAM%d Size = %" PRIx64 "\n", i,
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dram_regions_info.region[i].size);
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}
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rcw_porsr1 = bl31_image_ep_info.args.arg4;
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}
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if (bl_params->image_id == BL32_IMAGE_ID) {
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bl32_image_ep_info = *bl_params->ep_info;
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}
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if (bl_params->image_id == BL33_IMAGE_ID) {
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bl33_image_ep_info = *bl_params->ep_info;
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}
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bl_params = bl_params->next_params_info;
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}
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#endif /* TEST_BL31 */
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if (bl33_image_ep_info.pc == 0) {
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panic();
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}
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/*
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* perform basic initialization on the soc
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*/
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soc_init();
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}
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/*******************************************************************************
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* Perform any BL31 platform setup common to ARM standard platforms
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******************************************************************************/
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void bl31_platform_setup(void)
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{
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NOTICE("Welcome to %s BL31 Phase\n", BOARD);
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soc_platform_setup();
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/* Console logs gone missing as part going to
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* EL1 for initilizing Bl32 if present.
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* console flush is necessary to avoid it.
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*/
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(void)console_flush();
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}
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void bl31_plat_runtime_setup(void)
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{
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#ifdef LS_EL3_INTERRUPT_HANDLER
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ls_el3_interrupt_config();
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#endif
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soc_runtime_setup();
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}
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/*******************************************************************************
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* Perform the very early platform specific architectural setup shared between
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* ARM standard platforms. This only does basic initialization. Later
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* architectural setup (bl31_arch_setup()) does not do anything platform
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* specific.
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******************************************************************************/
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void bl31_plat_arch_setup(void)
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{
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ls_setup_page_tables(BL31_BASE,
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BL31_END - BL31_BASE,
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BL_CODE_BASE,
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BL_CODE_END,
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BL_RO_DATA_BASE,
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BL_RO_DATA_END
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#if USE_COHERENT_MEM
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, BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END
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#endif
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);
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enable_mmu_el3(0);
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}
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