Antonio Nino Diaz ed4fc6f026 Disable processor Cycle Counting in Secure state ... In a system with ARMv8.5-PMU implemented: - If EL3 is using AArch32, setting MDCR_EL3.SCCD to 1 disables counting in Secure state in PMCCNTR. - If EL3 is using AArch64, setting SDCR.SCCD to 1 disables counting in Secure state in PMCCNTR_EL0. So far this effect has been achieved by setting PMCR_EL0.DP (in AArch64) or PMCR.DP (in AArch32) to 1 instead, but this isn't considered secure as any EL can change that value. Change-Id: I82cbb3e48f2e5a55c44d9c4445683c5881ef1f6f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>		2019-02-18 17:03:16 +00:00
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arch.h	Disable processor Cycle Counting in Secure state	2019-02-18 17:03:16 +00:00
arch_features.h	drivers: generic_delay_timer: Assert presence of Generic Timer	2019-02-06 09:54:42 +00:00
arch_helpers.h	Helper function to read ID_AFR0_EL1 system register	2019-01-23 10:31:04 -08:00
asm_macros.S	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
assert_macros.S	Reorganize architecture-dependent header files	2019-01-04 10:43:16 +00:00
console_macros.S	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
el3_common_macros.S	Disable processor Cycle Counting in Secure state	2019-02-18 17:03:16 +00:00
smccc_helpers.h	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00