129 lines
3.1 KiB
ArmAsm
129 lines
3.1 KiB
ArmAsm
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <context.h>
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/* -----------------------------------------------------------------------------
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* Very simple stackless exception handlers used by the spm shim layer.
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* -----------------------------------------------------------------------------
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*/
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.globl spm_shim_exceptions_ptr
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vector_base spm_shim_exceptions_ptr, .spm_shim_exceptions
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/* -----------------------------------------------------
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* Current EL with SP0 : 0x0 - 0x200
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionSP0, .spm_shim_exceptions
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b .
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end_vector_entry SynchronousExceptionSP0
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vector_entry IrqSP0, .spm_shim_exceptions
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b .
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end_vector_entry IrqSP0
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vector_entry FiqSP0, .spm_shim_exceptions
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b .
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end_vector_entry FiqSP0
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vector_entry SErrorSP0, .spm_shim_exceptions
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b .
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end_vector_entry SErrorSP0
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/* -----------------------------------------------------
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* Current EL with SPx: 0x200 - 0x400
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionSPx, .spm_shim_exceptions
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b .
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end_vector_entry SynchronousExceptionSPx
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vector_entry IrqSPx, .spm_shim_exceptions
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b .
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end_vector_entry IrqSPx
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vector_entry FiqSPx, .spm_shim_exceptions
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b .
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end_vector_entry FiqSPx
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vector_entry SErrorSPx, .spm_shim_exceptions
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b .
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end_vector_entry SErrorSPx
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/* -----------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600. No exceptions
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* are handled since secure_partition does not implement
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* a lower EL
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionA64, .spm_shim_exceptions
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msr tpidr_el1, x30
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mrs x30, esr_el1
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ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x30, #EC_AARCH64_SVC
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b.eq do_smc
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cmp x30, #EC_AARCH32_SVC
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b.eq do_smc
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cmp x30, #EC_AARCH64_SYS
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b.eq handle_sys_trap
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/* Fail in all the other cases */
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b panic
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/* ---------------------------------------------
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* Tell SPM that we are done initialising
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* ---------------------------------------------
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*/
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do_smc:
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mrs x30, tpidr_el1
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smc #0
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eret
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/* AArch64 system instructions trap are handled as a panic for now */
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handle_sys_trap:
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panic:
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b panic
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end_vector_entry SynchronousExceptionA64
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vector_entry IrqA64, .spm_shim_exceptions
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b .
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end_vector_entry IrqA64
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vector_entry FiqA64, .spm_shim_exceptions
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b .
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end_vector_entry FiqA64
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vector_entry SErrorA64, .spm_shim_exceptions
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b .
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end_vector_entry SErrorA64
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/* -----------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionA32, .spm_shim_exceptions
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b .
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end_vector_entry SynchronousExceptionA32
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vector_entry IrqA32, .spm_shim_exceptions
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b .
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end_vector_entry IrqA32
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vector_entry FiqA32, .spm_shim_exceptions
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b .
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end_vector_entry FiqA32
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vector_entry SErrorA32, .spm_shim_exceptions
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b .
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end_vector_entry SErrorA32
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