287 lines
7.8 KiB
C
287 lines
7.8 KiB
C
/*
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* Copyright (c) 2022, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <mt_spm.h>
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#include <mt_spm_conservation.h>
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#include <mt_spm_internal.h>
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#include <mt_spm_rc_internal.h>
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#include <mt_spm_reg.h>
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#include <mt_spm_resource_req.h>
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#include <mt_spm_suspend.h>
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#include <plat_pm.h>
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#include <uart.h>
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#define SPM_SUSPEND_SLEEP_PCM_FLAG \
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(SPM_FLAG_DISABLE_INFRA_PDN | \
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SPM_FLAG_DISABLE_VCORE_DVS | \
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SPM_FLAG_DISABLE_VCORE_DFS | \
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SPM_FLAG_USE_SRCCLKENO2)
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#define SPM_SUSPEND_SLEEP_PCM_FLAG1 (0U)
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#define SPM_SUSPEND_PCM_FLAG \
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(SPM_FLAG_DISABLE_VCORE_DVS | \
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SPM_FLAG_DISABLE_VCORE_DFS)
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#define SPM_SUSPEND_PCM_FLAG1 (0U)
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#define __WAKE_SRC_FOR_SUSPEND_COMMON__ \
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(R12_PCM_TIMER | \
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R12_KP_IRQ_B | \
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R12_APWDT_EVENT_B | \
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R12_CONN2AP_SPM_WAKEUP_B | \
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R12_EINT_EVENT_B | \
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R12_CONN_WDT_IRQ_B | \
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R12_SSPM2SPM_WAKEUP_B | \
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R12_SCP2SPM_WAKEUP_B | \
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R12_ADSP2SPM_WAKEUP_B | \
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R12_USBX_CDSC_B | \
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R12_USBX_POWERDWN_B | \
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R12_SYS_TIMER_EVENT_B | \
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R12_EINT_EVENT_SECURE_B | \
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R12_SYS_CIRQ_IRQ_B | \
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R12_NNA_WAKEUP | \
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R12_REG_CPU_WAKEUP)
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#if defined(CFG_MICROTRUST_TEE_SUPPORT)
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#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__)
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#else
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#define WAKE_SRC_FOR_SUSPEND \
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(__WAKE_SRC_FOR_SUSPEND_COMMON__ | \
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R12_SEJ_EVENT_B)
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#endif
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static struct pwr_ctrl suspend_ctrl = {
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.wake_src = WAKE_SRC_FOR_SUSPEND,
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/* Auto-gen Start */
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/* SPM_AP_STANDBY_CON */
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.reg_wfi_op = 0,
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.reg_wfi_type = 0,
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.reg_mp0_cputop_idle_mask = 0,
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.reg_mp1_cputop_idle_mask = 0,
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.reg_mcusys_idle_mask = 0,
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.reg_md_apsrc_1_sel = 0,
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.reg_md_apsrc_0_sel = 0,
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.reg_conn_apsrc_sel = 0,
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/* SPM_SRC6_MASK */
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.reg_ccif_event_infra_req_mask_b = 0,
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.reg_ccif_event_apsrc_req_mask_b = 0,
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/* SPM_SRC_REQ */
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.reg_spm_apsrc_req = 0,
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.reg_spm_f26m_req = 0,
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.reg_spm_infra_req = 0,
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.reg_spm_vrf18_req = 0,
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.reg_spm_ddren_req = 0,
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.reg_spm_dvfs_req = 0,
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.reg_spm_sw_mailbox_req = 0,
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.reg_spm_sspm_mailbox_req = 0,
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.reg_spm_adsp_mailbox_req = 0,
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.reg_spm_scp_mailbox_req = 0,
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/* SPM_SRC_MASK */
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.reg_md_0_srcclkena_mask_b = 0,
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.reg_md_0_infra_req_mask_b = 0,
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.reg_md_0_apsrc_req_mask_b = 0,
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.reg_md_0_vrf18_req_mask_b = 0,
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.reg_md_0_ddren_req_mask_b = 0,
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.reg_md_1_srcclkena_mask_b = 0,
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.reg_md_1_infra_req_mask_b = 0,
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.reg_md_1_apsrc_req_mask_b = 0,
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.reg_md_1_vrf18_req_mask_b = 0,
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.reg_md_1_ddren_req_mask_b = 0,
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.reg_conn_srcclkena_mask_b = 1,
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.reg_conn_srcclkenb_mask_b = 0,
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.reg_conn_infra_req_mask_b = 1,
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.reg_conn_apsrc_req_mask_b = 1,
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.reg_conn_vrf18_req_mask_b = 1,
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.reg_conn_ddren_req_mask_b = 1,
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.reg_conn_vfe28_mask_b = 0,
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.reg_srcclkeni_srcclkena_mask_b = 1,
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.reg_srcclkeni_infra_req_mask_b = 1,
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.reg_infrasys_apsrc_req_mask_b = 0,
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.reg_infrasys_ddren_req_mask_b = 1,
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.reg_sspm_srcclkena_mask_b = 1,
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.reg_sspm_infra_req_mask_b = 1,
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.reg_sspm_apsrc_req_mask_b = 1,
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.reg_sspm_vrf18_req_mask_b = 1,
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.reg_sspm_ddren_req_mask_b = 1,
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/* SPM_SRC2_MASK */
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.reg_scp_srcclkena_mask_b = 1,
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.reg_scp_infra_req_mask_b = 1,
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.reg_scp_apsrc_req_mask_b = 1,
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.reg_scp_vrf18_req_mask_b = 1,
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.reg_scp_ddren_req_mask_b = 1,
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.reg_audio_dsp_srcclkena_mask_b = 1,
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.reg_audio_dsp_infra_req_mask_b = 1,
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.reg_audio_dsp_apsrc_req_mask_b = 1,
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.reg_audio_dsp_vrf18_req_mask_b = 1,
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.reg_audio_dsp_ddren_req_mask_b = 1,
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.reg_ufs_srcclkena_mask_b = 1,
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.reg_ufs_infra_req_mask_b = 1,
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.reg_ufs_apsrc_req_mask_b = 1,
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.reg_ufs_vrf18_req_mask_b = 1,
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.reg_ufs_ddren_req_mask_b = 1,
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.reg_disp0_apsrc_req_mask_b = 1,
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.reg_disp0_ddren_req_mask_b = 1,
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.reg_disp1_apsrc_req_mask_b = 1,
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.reg_disp1_ddren_req_mask_b = 1,
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.reg_gce_infra_req_mask_b = 1,
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.reg_gce_apsrc_req_mask_b = 1,
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.reg_gce_vrf18_req_mask_b = 1,
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.reg_gce_ddren_req_mask_b = 1,
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.reg_apu_srcclkena_mask_b = 0,
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.reg_apu_infra_req_mask_b = 0,
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.reg_apu_apsrc_req_mask_b = 0,
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.reg_apu_vrf18_req_mask_b = 0,
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.reg_apu_ddren_req_mask_b = 0,
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.reg_cg_check_srcclkena_mask_b = 0,
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.reg_cg_check_apsrc_req_mask_b = 0,
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.reg_cg_check_vrf18_req_mask_b = 0,
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.reg_cg_check_ddren_req_mask_b = 0,
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/* SPM_SRC3_MASK */
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.reg_dvfsrc_event_trigger_mask_b = 1,
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.reg_sw2spm_wakeup_mask_b = 0,
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.reg_adsp2spm_wakeup_mask_b = 0,
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.reg_sspm2spm_wakeup_mask_b = 0,
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.reg_scp2spm_wakeup_mask_b = 0,
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.reg_csyspwrup_ack_mask = 1,
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.reg_spm_reserved_srcclkena_mask_b = 0,
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.reg_spm_reserved_infra_req_mask_b = 0,
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.reg_spm_reserved_apsrc_req_mask_b = 0,
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.reg_spm_reserved_vrf18_req_mask_b = 0,
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.reg_spm_reserved_ddren_req_mask_b = 0,
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.reg_mcupm_srcclkena_mask_b = 0,
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.reg_mcupm_infra_req_mask_b = 0,
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.reg_mcupm_apsrc_req_mask_b = 0,
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.reg_mcupm_vrf18_req_mask_b = 0,
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.reg_mcupm_ddren_req_mask_b = 0,
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.reg_msdc0_srcclkena_mask_b = 1,
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.reg_msdc0_infra_req_mask_b = 1,
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.reg_msdc0_apsrc_req_mask_b = 1,
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.reg_msdc0_vrf18_req_mask_b = 1,
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.reg_msdc0_ddren_req_mask_b = 1,
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.reg_msdc1_srcclkena_mask_b = 1,
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.reg_msdc1_infra_req_mask_b = 1,
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.reg_msdc1_apsrc_req_mask_b = 1,
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.reg_msdc1_vrf18_req_mask_b = 1,
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.reg_msdc1_ddren_req_mask_b = 1,
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/* SPM_SRC4_MASK */
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.reg_ccif_event_srcclkena_mask_b = 0,
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.reg_bak_psri_srcclkena_mask_b = 0,
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.reg_bak_psri_infra_req_mask_b = 0,
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.reg_bak_psri_apsrc_req_mask_b = 0,
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.reg_bak_psri_vrf18_req_mask_b = 0,
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.reg_bak_psri_ddren_req_mask_b = 0,
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.reg_dramc_md32_infra_req_mask_b = 0,
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.reg_dramc_md32_vrf18_req_mask_b = 0,
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.reg_conn_srcclkenb2pwrap_mask_b = 0,
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.reg_dramc_md32_apsrc_req_mask_b = 0,
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/* SPM_SRC5_MASK */
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.reg_mcusys_merge_apsrc_req_mask_b = 0x83,
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.reg_mcusys_merge_ddren_req_mask_b = 0x83,
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.reg_afe_srcclkena_mask_b = 1,
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.reg_afe_infra_req_mask_b = 1,
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.reg_afe_apsrc_req_mask_b = 1,
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.reg_afe_vrf18_req_mask_b = 1,
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.reg_afe_ddren_req_mask_b = 1,
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.reg_msdc2_srcclkena_mask_b = 0,
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.reg_msdc2_infra_req_mask_b = 0,
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.reg_msdc2_apsrc_req_mask_b = 0,
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.reg_msdc2_vrf18_req_mask_b = 0,
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.reg_msdc2_ddren_req_mask_b = 0,
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/* SPM_WAKEUP_EVENT_MASK */
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.reg_wakeup_event_mask = 0x1383213,
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/* SPM_WAKEUP_EVENT_EXT_MASK */
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.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
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/* SPM_SRC7_MASK */
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.reg_pcie_srcclkena_mask_b = 0,
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.reg_pcie_infra_req_mask_b = 0,
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.reg_pcie_apsrc_req_mask_b = 0,
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.reg_pcie_vrf18_req_mask_b = 0,
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.reg_pcie_ddren_req_mask_b = 0,
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.reg_dpmaif_srcclkena_mask_b = 1,
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.reg_dpmaif_infra_req_mask_b = 1,
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.reg_dpmaif_apsrc_req_mask_b = 1,
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.reg_dpmaif_vrf18_req_mask_b = 1,
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.reg_dpmaif_ddren_req_mask_b = 1,
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/* Auto-gen End */
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/*sw flag setting */
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.pcm_flags = SPM_SUSPEND_PCM_FLAG,
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.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1,
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};
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struct spm_lp_scen __spm_suspend = {
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.pwrctrl = &suspend_ctrl,
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};
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int mt_spm_suspend_mode_set(int mode)
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{
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if (mode == MT_SPM_SUSPEND_SLEEP) {
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suspend_ctrl.pcm_flags = SPM_SUSPEND_SLEEP_PCM_FLAG;
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suspend_ctrl.pcm_flags1 = SPM_SUSPEND_SLEEP_PCM_FLAG1;
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} else {
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suspend_ctrl.pcm_flags = SPM_SUSPEND_PCM_FLAG;
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suspend_ctrl.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1;
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}
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return 0;
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}
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int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
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unsigned int resource_req)
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{
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/* If FMAudio / ADSP is active, change to sleep suspend mode */
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if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
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mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SLEEP);
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}
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/* Notify MCUPM that device is going suspend flow */
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mmio_write_32(MCUPM_MBOX_OFFSET_PDN, MCUPM_POWER_DOWN);
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/* Notify UART to sleep */
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mt_uart_save();
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return spm_conservation(state_id, ext_opand,
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&__spm_suspend, resource_req);
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}
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void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
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struct wake_status **status)
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{
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spm_conservation_finish(state_id, ext_opand, &__spm_suspend, status);
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/* Notify UART to wakeup */
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mt_uart_restore();
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/* Notify MCUPM that device leave suspend */
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mmio_write_32(MCUPM_MBOX_OFFSET_PDN, 0);
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/* If FMAudio / ADSP is active, change back to suspend mode */
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if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
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mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SYSTEM_PDN);
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}
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}
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void mt_spm_suspend_init(void)
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{
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spm_conservation_pwrctrl_init(__spm_suspend.pwrctrl);
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}
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