Louis Mayencourt 508d71108a Add workaround for errata 1130799 for Cortex-A76 ... TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page aggregated address translation data in the L2 TLB might cause corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to prevent this. Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>		2019-02-26 16:21:06 +00:00
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aarch32	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
aarch64	Add workaround for errata 1130799 for Cortex-A76	2019-02-26 16:21:06 +00:00
cpu-ops.mk	Add workaround for errata 1130799 for Cortex-A76	2019-02-26 16:21:06 +00:00
errata_report.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00