Louis Mayencourt 5f5d1ed7d5 Add workaround for errata 764081 of Cortex-A75 ... Implicit Error Synchronization Barrier (IESB) might not be correctly generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all expection levels. Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>		2019-02-26 15:53:57 +00:00
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context.S	Add support for dynamic mitigation for CVE-2018-3639	2018-05-23 12:45:48 +01:00
context_mgmt.c	Add workaround for errata 764081 of Cortex-A75	2019-02-26 15:53:57 +00:00
cpu_data.S	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00