108 lines
3.2 KiB
C
108 lines
3.2 KiB
C
/*
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* Copyright (c) 2019, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef GIC600_MULTICHIP_PRIVATE_H
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#define GIC600_MULTICHIP_PRIVATE_H
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#include <drivers/arm/gic600_multichip.h>
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#include "gicv3_private.h"
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/* GIC600 GICD multichip related offsets */
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#define GICD_CHIPSR U(0xC000)
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#define GICD_DCHIPR U(0xC004)
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#define GICD_CHIPR U(0xC008)
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/* GIC600 GICD multichip related masks */
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#define GICD_CHIPRx_PUP_BIT BIT_64(1)
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#define GICD_CHIPRx_SOCKET_STATE BIT_64(0)
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#define GICD_DCHIPR_PUP_BIT BIT_32(0)
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#define GICD_CHIPSR_RTS_MASK (BIT_32(4) | BIT_32(5))
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/* GIC600 GICD multichip related shifts */
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#define GICD_CHIPRx_ADDR_SHIFT 16
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#define GICD_CHIPSR_RTS_SHIFT 4
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#define GICD_DCHIPR_RT_OWNER_SHIFT 4
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/*
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* If GIC v4 extension is enabled, then use SPI macros specific to GIC-Clayton.
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* Other shifts and mask remains same between GIC-600 and GIC-Clayton.
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*/
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#if GIC_ENABLE_V4_EXTN
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#define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 9
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#define GICD_CHIPRx_SPI_BLOCKS_SHIFT 3
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#else
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#define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 10
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#define GICD_CHIPRx_SPI_BLOCKS_SHIFT 5
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#endif
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#define GICD_CHIPSR_RTS_STATE_DISCONNECTED U(0)
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#define GICD_CHIPSR_RTS_STATE_UPDATING U(1)
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#define GICD_CHIPSR_RTS_STATE_CONSISTENT U(2)
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/* SPI interrupt id minimum and maximum range */
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#define GIC600_SPI_ID_MIN 32
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#define GIC600_SPI_ID_MAX 960
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/* Number of retries for PUP update */
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#define GICD_PUP_UPDATE_RETRIES 10000
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#define SPI_MIN_INDEX 0
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#define SPI_MAX_INDEX 1
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#define SPI_BLOCK_MIN_VALUE(spi_id_min) \
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(((spi_id_min) - GIC600_SPI_ID_MIN) / \
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GIC600_SPI_ID_MIN)
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#define SPI_BLOCKS_VALUE(spi_id_min, spi_id_max) \
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(((spi_id_max) - (spi_id_min) + 1) / \
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GIC600_SPI_ID_MIN)
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#define GICD_CHIPR_VALUE(chip_addr, spi_block_min, spi_blocks) \
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(((chip_addr) << GICD_CHIPRx_ADDR_SHIFT) | \
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((spi_block_min) << GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT) | \
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((spi_blocks) << GICD_CHIPRx_SPI_BLOCKS_SHIFT))
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/*
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* Multichip data assertion macros
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*/
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/* Set bits from 0 to ((spi_id_max + 1) / 32) */
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#define SPI_BLOCKS_TILL_MAX(spi_id_max) ((1 << (((spi_id_max) + 1) >> 5)) - 1)
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/* Set bits from 0 to (spi_id_min / 32) */
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#define SPI_BLOCKS_TILL_MIN(spi_id_min) ((1 << ((spi_id_min) >> 5)) - 1)
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/* Set bits from (spi_id_min / 32) to ((spi_id_max + 1) / 32) */
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#define BLOCKS_OF_32(spi_id_min, spi_id_max) \
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SPI_BLOCKS_TILL_MAX(spi_id_max) ^ \
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SPI_BLOCKS_TILL_MIN(spi_id_min)
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/*******************************************************************************
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* GIC-600 multichip operation related helper functions
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******************************************************************************/
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static inline uint32_t read_gicd_dchipr(uintptr_t base)
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{
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return mmio_read_32(base + GICD_DCHIPR);
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}
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static inline uint64_t read_gicd_chipr_n(uintptr_t base, uint8_t n)
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{
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return mmio_read_64(base + (GICD_CHIPR + (8U * n)));
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}
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static inline uint32_t read_gicd_chipsr(uintptr_t base)
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{
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return mmio_read_32(base + GICD_CHIPSR);
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}
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static inline void write_gicd_dchipr(uintptr_t base, uint32_t val)
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{
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mmio_write_32(base + GICD_DCHIPR, val);
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}
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static inline void write_gicd_chipr_n(uintptr_t base, uint8_t n, uint64_t val)
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{
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mmio_write_64(base + (GICD_CHIPR + (8U * n)), val);
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}
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#endif /* GIC600_MULTICHIP_PRIVATE_H */
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