109 lines
3.3 KiB
ArmAsm
109 lines
3.3 KiB
ArmAsm
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <memctrl_v2.h>
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#include <tegra_def.h>
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#define TEGRA186_SMMU_CTX_SIZE 0x420
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.align 4
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.globl tegra186_cpu_reset_handler
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/* CPU reset handler routine */
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func tegra186_cpu_reset_handler
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/*
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* The Memory Controller loses state during System Suspend. We
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* use this information to decide if the reset handler is running
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* after a System Suspend. Resume from system suspend requires
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* restoring the entire state from TZDRAM to TZRAM.
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*/
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mov x1, #TEGRA_MC_BASE
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ldr w0, [x1, #MC_SECURITY_CFG3_0]
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lsl x0, x0, #32
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ldr w0, [x1, #MC_SECURITY_CFG0_0]
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adr x1, tegra186_cpu_reset_handler
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cmp x0, x1
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beq boot_cpu
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/* resume from system suspend */
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mov x0, #BL31_BASE
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adr x1, __tegra186_cpu_reset_handler_end
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adr x2, __tegra186_cpu_reset_handler_data
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ldr x2, [x2, #8]
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/* memcpy16 */
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m_loop16:
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cmp x2, #16
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b.lt m_loop1
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ldp x3, x4, [x1], #16
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stp x3, x4, [x0], #16
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sub x2, x2, #16
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b m_loop16
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/* copy byte per byte */
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m_loop1:
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cbz x2, boot_cpu
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ldrb w3, [x1], #1
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strb w3, [x0], #1
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subs x2, x2, #1
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b.ne m_loop1
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boot_cpu:
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adr x0, __tegra186_cpu_reset_handler_data
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ldr x0, [x0]
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br x0
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endfunc tegra186_cpu_reset_handler
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/*
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* Tegra186 reset data (offset 0x0 - 0x430)
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*
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* 0x000: secure world's entrypoint
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* 0x008: BL31 size (RO + RW)
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* 0x00C: SMMU context start
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* 0x42C: SMMU context end
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*/
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.align 4
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.type __tegra186_cpu_reset_handler_data, %object
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.globl __tegra186_cpu_reset_handler_data
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__tegra186_cpu_reset_handler_data:
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.quad tegra_secure_entrypoint
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.quad __BL31_END__ - BL31_BASE
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.rept TEGRA186_SMMU_CTX_SIZE
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.quad 0
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.endr
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.size __tegra186_cpu_reset_handler_data, \
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. - __tegra186_cpu_reset_handler_data
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.align 4
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.globl __tegra186_cpu_reset_handler_end
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__tegra186_cpu_reset_handler_end:
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