Manish V Badarkhe cb55615c50 el3_runtime: Rearrange context offset of EL1 sys registers ... SCTLR and TCR registers of EL1 plays role in enabling/disabling of page table walk for lower ELs (EL0 and EL1). Hence re-arranged EL1 context offsets to have SCTLR and TCR registers values one after another in the stack so that these registers values can be saved and restored using stp and ldp instruction respectively. Change-Id: Iaa28fd9eba82a60932b6b6d85ec8857a9acd5f8b Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>		2020-08-18 10:49:27 +01:00
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aarch32	coverity: fix MISRA violations	2020-02-18 10:47:46 -06:00
aarch64	el3_runtime: Rearrange context offset of EL1 sys registers	2020-08-18 10:49:27 +01:00
context_mgmt.h	include: fixup 'cm_setup_context' prototype	2020-04-01 14:46:42 -07:00
cpu_data.h	Refactor ARMv8.3 Pointer Authentication support code	2019-09-13 14:11:59 +01:00
pubsub.h	Merge pull request #1751 from vwadekar/tegra-scatter-file-support	2019-03-01 11:23:58 +00:00
pubsub_events.h	Switch AARCH32/AARCH64 to __aarch64__	2019-08-01 13:45:03 -07:00