Varun Wadekar 51a5e593d6 Tegra210: Enable WDT_CPU interrupt for FIQ Debugger ... This patch enables the watchdog timer's interrupt as an FIQ interrupt to the CPU. The interrupt generated by the watchdog is connected to the flow controller for power management reasons, and needs to be routed to the GICD for it to reach the CPU. Change-Id: I9437b516da2c5d763eca72694ed7f3c7389b3d9e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2019-01-31 08:47:29 -08:00
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drivers/se	Tegra210_B01: SC7: Select RNG mode based on ECID	2019-01-18 09:21:51 -08:00
plat_psci_handlers.c	Tegra: bpmp: return error if BPMP init fails	2019-01-23 10:32:51 -08:00
plat_secondary.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
plat_setup.c	Tegra210: Enable WDT_CPU interrupt for FIQ Debugger	2019-01-31 08:47:29 -08:00
platform_t210.mk	Tegra: fiq_glue: support to handle LEGACY_FIQ PPIs for Tegra SoCs	2019-01-31 08:46:41 -08:00