529b541e8b
On TI platforms the UART is disabled by default and must be explicitly enabled using the MDR1 register. NOTE: The original definition of http://www.ti.com/lit/ds/symlink/pc16550d.pdf has no MDR register, but many TI SoCs implementing 16550 do have a quirky MDR register implemented. So, this should be enabled with TI_16550_MDR_QUIRK NOTE: In such implementation, the CSR register does not exist. Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> |
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| .. | ||
| arm | ||
| auth | ||
| cadence/uart | ||
| console | ||
| coreboot/cbmem_console/aarch64 | ||
| delay_timer | ||
| emmc | ||
| gpio | ||
| io | ||
| partition | ||
| synopsys | ||
| ti/uart | ||
| ufs | ||