530a5cbccb
* changes: Tegra194: add support to reset GPU Tegra194: memctrl: fix logic to check TZDRAM config register access Tegra: introduce plat_enable_console() Tegra: include: drivers: introduce spe.h Tegra194: update nvg header to v6.4 Tegra194: mce: enable strict checking Tegra194: CC6 state from last offline CPU in the cluster Tegra194: console driver compilation from platform makefiles Tegra194: memctrl: platform handler for TZDRAM setup Tegra194: memctrl: override SE client as coherent Tegra194: save system suspend entry marker to TZDRAM Tegra194: helper functions for CPU rst handler and SMMU ctx offset Tegra194: cleanup references to Tegra186 Tegra194: mce: display NVG header version during boot Tegra194: mce: fix cg_cstate encoding format Tegra194: drivers: SE and RNG1/PKA1 context save support Tegra194: rename secure scratch register macros Tegra194: SiP: Fix Rule 8.4 and Rule 10.4 violation Tegra194: mce: remove unsupported functionality Tegra194: sanity check target cluster during core power on Tegra194: fix defects flagged by MISRA scan Tegra194: mce: fix defects flagged by MISRA scan Tegra194: remove the GPU reset register macro Tegra194: MC registers to allow CPU accesses to TZRAM Tegra194: increase MAX_MMAP_REGIONS macro value Tegra194: update nvg header to v6.1 Tegra194: update cache operations supported by the ROC Tegra194: memctrl: platform handlers to reprogram MSS Tegra194: core and cluster count values Tegra194: correct the TEGRA_CAR_RESET_BASE macro value Tegra194: add MC_SECURITY mask defines Tegra194: Update wake mask, wake time for cpu offlining Tegra194: program stream ids for XUSB Tegra194: Update checks for c-state stats Tegra194: smmu: fix mask for board revision id Tegra194: smmu: ISO support Tegra194: Initialize smmu on system suspend exit Tegra194: Update cpu core-id calculation Tegra194: read-modify-write ACTLR_ELx registers Tegra194: Enable fake system suspend Tegra194: convert 'target_cpu' and 'target_cluster' to 32-bits Tegra194: platform support for memctrl/smmu drivers Tegra194: Support for cpu suspend |
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| docs | ||
| drivers | ||
| fdts | ||
| include | ||
| lib | ||
| make_helpers | ||
| plat | ||
| services | ||
| tools | ||
| .checkpatch.conf | ||
| .editorconfig | ||
| .gitignore | ||
| Makefile | ||
| dco.txt | ||
| license.rst | ||
| readme.rst | ||
readme.rst
Trusted Firmware-A
Trusted Firmware-A (TF-A) is a reference implementation of secure world software for Arm A-Profile architectures (Armv8-A and Armv7-A), including an Exception Level 3 (EL3) Secure Monitor. It provides a suitable starting point for productization of secure world boot and runtime firmware, in either the AArch32 or AArch64 execution states.
TF-A implements Arm interface standards, including:
- Power State Coordination Interface (PSCI)
- Trusted Board Boot Requirements CLIENT (TBBR-CLIENT)
- SMC Calling Convention
- System Control and Management Interface (SCMI)
- Software Delegated Exception Interface (SDEI)
The code is designed to be portable and reusable across hardware platforms and software models that are based on the Armv8-A and Armv7-A architectures.
In collaboration with interested parties, we will continue to enhance TF-A with reference implementations of Arm standards to benefit developers working with Armv7-A and Armv8-A TrustZone technology.
Users are encouraged to do their own security validation, including penetration testing, on any secure world code derived from TF-A.
More Info and Documentation
To find out more about Trusted Firmware-A, please view the full documentation that is available through trustedfirmware.org.
Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.