Sandrine Bailleux 54035fc467 Disable non-temporal hint on Cortex-A53/57 ... The LDNP/STNP instructions as implemented on Cortex-A53 and Cortex-A57 do not behave in a way most programmers expect, and will most probably result in a significant speed degradation to any code that employs them. The ARMv8-A architecture (see Document ARM DDI 0487A.h, section D3.4.3) allows cores to ignore the non-temporal hint and treat LDNP/STNP as LDP/STP instead. This patch introduces 2 new build flags: A53_DISABLE_NON_TEMPORAL_HINT and A57_DISABLE_NON_TEMPORAL_HINT to enforce this behaviour on Cortex-A53 and Cortex-A57. They are enabled by default. The string printed in debug builds when a specific CPU errata workaround is compiled in but skipped at runtime has been generalised, so that it can be reused for the non-temporal hint use case as well. Change-Id: I3e354f4797fd5d3959872a678e160322b13867a1		2016-02-08 09:31:18 +00:00
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aarch64	Disable non-temporal hint on Cortex-A53/57	2016-02-08 09:31:18 +00:00
cpu-ops.mk	Disable non-temporal hint on Cortex-A53/57	2016-02-08 09:31:18 +00:00