137 lines
3.6 KiB
C
137 lines
3.6 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __BOARD_ARM_DEF_H__
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#define __BOARD_ARM_DEF_H__
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#include <v2m_def.h>
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/*
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* Required platform porting definitions common to all ARM
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* development platforms
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*/
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/* Size of cacheable stacks */
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#if defined(IMAGE_BL1)
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#if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE 0x1000
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#else
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# define PLATFORM_STACK_SIZE 0x440
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#endif
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#elif defined(IMAGE_BL2)
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# if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE 0x1000
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# else
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# define PLATFORM_STACK_SIZE 0x400
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# endif
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#elif defined(IMAGE_BL2U)
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# define PLATFORM_STACK_SIZE 0x200
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#elif defined(IMAGE_BL31)
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# define PLATFORM_STACK_SIZE 0x400
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#elif defined(IMAGE_BL32)
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# define PLATFORM_STACK_SIZE 0x440
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#endif
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/*
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* The constants below are not optimised for memory usage. Platforms that wish
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* to optimise these constants should set `ARM_BOARD_OPTIMISE_MEM` to 1 and
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* provide there own values.
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*/
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#if !ARM_BOARD_OPTIMISE_MEM
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/*
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* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
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* plat_arm_mmap array defined for each BL stage.
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*
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* Provide relatively optimised values for the runtime images (BL31 and BL32).
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* Optimisation is less important for the other, transient boot images so a
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* common, maximum value is used across these images.
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*
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* They are also used for the dynamically mapped regions in the images that
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* enable dynamic memory mapping.
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*/
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#if defined(IMAGE_BL31)
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# if ENABLE_SPM
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# define PLAT_ARM_MMAP_ENTRIES 9
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# define MAX_XLAT_TABLES 7
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# define PLAT_SP_IMAGE_MMAP_REGIONS 7
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# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10
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# else
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# define PLAT_ARM_MMAP_ENTRIES 7
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# define MAX_XLAT_TABLES 5
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# endif
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#elif defined(IMAGE_BL32)
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# define PLAT_ARM_MMAP_ENTRIES 7
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# define MAX_XLAT_TABLES 5
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#else
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# define PLAT_ARM_MMAP_ENTRIES 11
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# define MAX_XLAT_TABLES 5
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#endif
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/*
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* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
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* plus a little space for growth.
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*/
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#define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000
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/*
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* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
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* little space for growth.
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*/
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#if TRUSTED_BOARD_BOOT
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# define PLAT_ARM_MAX_BL2_SIZE 0x1E000
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#else
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# define PLAT_ARM_MAX_BL2_SIZE 0xF000
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#endif
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/*
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* PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a
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* little space for growth.
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*/
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#if ENABLE_SPM
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#define PLAT_ARM_MAX_BL31_SIZE 0x28000
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#else
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#define PLAT_ARM_MAX_BL31_SIZE 0x1D000
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#endif
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#ifdef AARCH32
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/*
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* PLAT_ARM_MAX_BL32_SIZE is calculated for SP_MIN as the AArch32 Secure
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* Payload.
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*/
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# define PLAT_ARM_MAX_BL32_SIZE 0x1D000
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#endif
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#endif /* ARM_BOARD_OPTIMISE_MEM */
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */
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/* Reserve the last block of flash for PSCI MEM PROTECT flag */
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#define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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/* PSCI memory protect definitions:
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* This variable is stored in a non-secure flash because some ARM reference
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* platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
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* support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
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*/
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#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
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V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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/*
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* Map mem_protect flash region with read and write permissions
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*/
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#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \
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V2M_FLASH_BLOCK_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#endif /* __BOARD_ARM_DEF_H__ */
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