495 lines
16 KiB
C
495 lines
16 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __ARM_DEF_H__
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#define __ARM_DEF_H__
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#include <arch.h>
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#include <common_def.h>
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#include <gic_common.h>
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#include <interrupt_props.h>
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#include <platform_def.h>
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#include <tbbr_img_def.h>
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#include <utils_def.h>
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#include <xlat_tables_defs.h>
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/******************************************************************************
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* Definitions common to all ARM standard platforms
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*****************************************************************************/
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/* Special value used to verify platform parameters from BL2 to BL31 */
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#define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define ARM_SYSTEM_COUNT 1
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#define ARM_CACHE_WRITEBACK_SHIFT 6
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/*
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* Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
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* power levels have a 1:1 mapping with the MPIDR affinity levels.
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*/
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#define ARM_PWR_LVL0 MPIDR_AFFLVL0
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#define ARM_PWR_LVL1 MPIDR_AFFLVL1
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#define ARM_PWR_LVL2 MPIDR_AFFLVL2
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/*
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* Macros for local power states in ARM platforms encoded by State-ID field
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* within the power-state parameter.
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*/
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/* Local power state for power domains in Run state. */
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#define ARM_LOCAL_STATE_RUN 0
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/* Local power state for retention. Valid only for CPU power domains */
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#define ARM_LOCAL_STATE_RET 1
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/* Local power state for OFF/power-down. Valid for CPU and cluster power
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domains */
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#define ARM_LOCAL_STATE_OFF 2
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/* Memory location options for TSP */
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#define ARM_TRUSTED_SRAM_ID 0
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#define ARM_TRUSTED_DRAM_ID 1
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#define ARM_DRAM_ID 2
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/* The first 4KB of Trusted SRAM are used as shared memory */
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#define ARM_TRUSTED_SRAM_BASE 0x04000000
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#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE
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#define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
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/* The remaining Trusted SRAM is used to load the BL images */
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#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
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ARM_SHARED_RAM_SIZE)
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#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
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ARM_SHARED_RAM_SIZE)
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/*
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* The top 16MB of DRAM1 is configured as secure access only using the TZC
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* - SCP TZC DRAM: If present, DRAM reserved for SCP use
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* - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
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*/
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#define ARM_TZC_DRAM1_SIZE ULL(0x01000000)
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#define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
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ARM_DRAM1_SIZE - \
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ARM_SCP_TZC_DRAM1_SIZE)
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#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE
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#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \
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ARM_SCP_TZC_DRAM1_SIZE - 1)
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/*
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* Define a 2MB region within the TZC secured DRAM for use by EL3 runtime
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* firmware. This region is meant to be NOLOAD and will not be zero
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* initialized. Data sections with the attribute `arm_el3_tzc_dram` will be
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* placed here.
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*/
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#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE)
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#define ARM_EL3_TZC_DRAM1_SIZE ULL(0x00200000) /* 2 MB */
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#define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \
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ARM_EL3_TZC_DRAM1_SIZE - 1)
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#define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
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ARM_DRAM1_SIZE - \
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ARM_TZC_DRAM1_SIZE)
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#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \
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(ARM_SCP_TZC_DRAM1_SIZE + \
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ARM_EL3_TZC_DRAM1_SIZE))
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#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
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ARM_AP_TZC_DRAM1_SIZE - 1)
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/* Define the Access permissions for Secure peripherals to NS_DRAM */
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#if ARM_CRYPTOCELL_INTEG
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/*
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* Allow Secure peripheral to read NS DRAM when integrated with CryptoCell.
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* This is required by CryptoCell to authenticate BL33 which is loaded
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* into the Non Secure DDR.
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*/
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#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD
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#else
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#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE
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#endif
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#ifdef SPD_opteed
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/*
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* BL2 needs to map 4MB at the end of TZC_DRAM1 in order to
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* load/authenticate the trusted os extra image. The first 512KB of
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* TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading
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* for OPTEE is paged image which only include the paging part using
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* virtual memory but without "init" data. OPTEE will copy the "init" data
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* (from pager image) to the first 512KB of TZC_DRAM, and then copy the
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* extra image behind the "init" data.
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*/
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#define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \
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ARM_AP_TZC_DRAM1_SIZE - \
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ARM_OPTEE_PAGEABLE_LOAD_SIZE)
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#define ARM_OPTEE_PAGEABLE_LOAD_SIZE 0x400000
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#define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \
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ARM_OPTEE_PAGEABLE_LOAD_BASE, \
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ARM_OPTEE_PAGEABLE_LOAD_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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/*
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* Map the memory for the OP-TEE core (also known as OP-TEE pager when paging
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* support is enabled).
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*/
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#define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \
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BL32_BASE, \
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BL32_LIMIT - BL32_BASE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#endif /* SPD_opteed */
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#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
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#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
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ARM_TZC_DRAM1_SIZE)
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#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
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ARM_NS_DRAM1_SIZE - 1)
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#define ARM_DRAM1_BASE ULL(0x80000000)
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#define ARM_DRAM1_SIZE ULL(0x80000000)
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#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
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ARM_DRAM1_SIZE - 1)
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#define ARM_DRAM2_BASE ULL(0x880000000)
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#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
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#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
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ARM_DRAM2_SIZE - 1)
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#define ARM_IRQ_SEC_PHY_TIMER 29
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#define ARM_IRQ_SEC_SGI_0 8
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#define ARM_IRQ_SEC_SGI_1 9
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#define ARM_IRQ_SEC_SGI_2 10
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#define ARM_IRQ_SEC_SGI_3 11
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#define ARM_IRQ_SEC_SGI_4 12
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#define ARM_IRQ_SEC_SGI_5 13
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#define ARM_IRQ_SEC_SGI_6 14
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#define ARM_IRQ_SEC_SGI_7 15
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/*
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* List of secure interrupts are deprecated, but are retained only to support
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* legacy configurations.
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*/
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#define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \
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ARM_IRQ_SEC_SGI_1, \
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ARM_IRQ_SEC_SGI_2, \
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ARM_IRQ_SEC_SGI_3, \
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ARM_IRQ_SEC_SGI_4, \
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ARM_IRQ_SEC_SGI_5, \
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ARM_IRQ_SEC_SGI_7
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#define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \
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ARM_IRQ_SEC_SGI_6
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/*
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* Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define ARM_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE)
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#define ARM_G0_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE)
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#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
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ARM_SHARED_RAM_BASE, \
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ARM_SHARED_RAM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
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ARM_NS_DRAM1_BASE, \
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ARM_NS_DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \
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ARM_DRAM2_BASE, \
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ARM_DRAM2_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#ifdef SPD_tspd
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#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
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TSP_SEC_MEM_BASE, \
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TSP_SEC_MEM_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#endif
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#if ARM_BL31_IN_DRAM
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#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
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BL31_BASE, \
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PLAT_ARM_MAX_BL31_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#endif
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#define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \
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ARM_EL3_TZC_DRAM1_BASE, \
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ARM_EL3_TZC_DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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/*
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* The number of regions like RO(code), coherent and data required by
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* different BL stages which need to be mapped in the MMU.
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*/
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#if USE_COHERENT_MEM
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#define ARM_BL_REGIONS 3
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#else
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#define ARM_BL_REGIONS 2
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#endif
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#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
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ARM_BL_REGIONS)
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/* Memory mapped Generic timer interfaces */
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#define ARM_SYS_CNTCTL_BASE 0x2a430000
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#define ARM_SYS_CNTREAD_BASE 0x2a800000
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#define ARM_SYS_TIMCTL_BASE 0x2a810000
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#define ARM_CONSOLE_BAUDRATE 115200
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/* Trusted Watchdog constants */
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#define ARM_SP805_TWDG_BASE 0x2a490000
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#define ARM_SP805_TWDG_CLK_HZ 32768
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/* The TBBR document specifies a watchdog timeout of 256 seconds. SP805
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* asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */
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#define ARM_TWDG_TIMEOUT_SEC 128
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#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \
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ARM_TWDG_TIMEOUT_SEC)
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/******************************************************************************
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* Required platform porting definitions common to all ARM standard platforms
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*****************************************************************************/
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/*
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* We need to access DRAM2 from BL2 for PSCI_MEM_PROTECT for
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* AArch64 builds
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*/
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#ifdef AARCH64
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 36)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 36)
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#else
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
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#endif
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/*
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* This macro defines the deepest retention state possible. A higher state
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* id will represent an invalid or a power down state.
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*/
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#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET
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/*
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* This macro defines the deepest power down states possible. Any state ID
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* higher than this is invalid.
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*/
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#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT)
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/*******************************************************************************
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* BL1 specific defines.
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* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
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* addresses.
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******************************************************************************/
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#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE
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#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \
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+ PLAT_ARM_TRUSTED_ROM_SIZE)
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/*
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* Put BL1 RW at the top of the Trusted SRAM.
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*/
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#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
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ARM_BL_RAM_SIZE - \
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PLAT_ARM_MAX_BL1_RW_SIZE)
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#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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/*******************************************************************************
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* BL2 specific defines.
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******************************************************************************/
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#if ARM_BL31_IN_DRAM
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/*
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* For AArch64 BL31 is loaded in the DRAM.
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* Put BL2 just below BL1.
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*/
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#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
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#define BL2_LIMIT BL1_RW_BASE
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#elif defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME
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/*
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* Put BL2 just below BL32.
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*/
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#define BL2_BASE (BL32_BASE - PLAT_ARM_MAX_BL2_SIZE)
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#define BL2_LIMIT BL32_BASE
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#else
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/*
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* Put BL2 just below BL31.
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*/
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#define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE)
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#define BL2_LIMIT BL31_BASE
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#endif
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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#if ARM_BL31_IN_DRAM
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/*
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* Put BL31 at the bottom of TZC secured DRAM
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*/
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#define BL31_BASE ARM_AP_TZC_DRAM1_BASE
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#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
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PLAT_ARM_MAX_BL31_SIZE)
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#elif (RESET_TO_BL31)
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/*
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* Put BL31_BASE in the middle of the Trusted SRAM.
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*/
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#define BL31_BASE (ARM_TRUSTED_SRAM_BASE + \
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(PLAT_ARM_TRUSTED_SRAM_SIZE >> 1))
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#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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#else
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/*
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* Put BL31 at the top of the Trusted SRAM.
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*/
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#define BL31_BASE (ARM_BL_RAM_BASE + \
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ARM_BL_RAM_SIZE - \
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PLAT_ARM_MAX_BL31_SIZE)
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#define BL31_PROGBITS_LIMIT BL1_RW_BASE
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#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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#endif
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#if defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME
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/*******************************************************************************
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* BL32 specific defines for EL3 runtime in AArch32 mode
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******************************************************************************/
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# if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME
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/* SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM to BL32 */
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# define BL32_BASE ARM_BL_RAM_BASE
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# define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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# else
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/* Put BL32 at the top of the Trusted SRAM.*/
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# define BL32_BASE (ARM_BL_RAM_BASE + \
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ARM_BL_RAM_SIZE - \
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PLAT_ARM_MAX_BL32_SIZE)
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# define BL32_PROGBITS_LIMIT BL1_RW_BASE
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# define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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# endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */
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#else
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/*******************************************************************************
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* BL32 specific defines for EL3 runtime in AArch64 mode
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******************************************************************************/
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/*
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* On ARM standard platforms, the TSP can execute from Trusted SRAM,
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* Trusted DRAM (if available) or the DRAM region secured by the TrustZone
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* controller.
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*/
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# if ENABLE_SPM
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# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
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# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000))
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# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
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# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
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ARM_AP_TZC_DRAM1_SIZE)
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# elif ARM_BL31_IN_DRAM
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# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \
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PLAT_ARM_MAX_BL31_SIZE)
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# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \
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PLAT_ARM_MAX_BL31_SIZE)
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# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \
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PLAT_ARM_MAX_BL31_SIZE)
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# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
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ARM_AP_TZC_DRAM1_SIZE)
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# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
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# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE
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# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE
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# define TSP_PROGBITS_LIMIT BL2_BASE
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# define BL32_BASE ARM_BL_RAM_BASE
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# define BL32_LIMIT BL31_BASE
|
|
# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID
|
|
# define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE
|
|
# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE
|
|
# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE
|
|
# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \
|
|
+ (1 << 21))
|
|
# elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
|
|
# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
|
|
# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
|
|
# define BL32_BASE ARM_AP_TZC_DRAM1_BASE
|
|
# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
|
|
ARM_AP_TZC_DRAM1_SIZE)
|
|
# else
|
|
# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
|
|
# endif
|
|
#endif /* AARCH32 || JUNO_AARCH32_EL3_RUNTIME */
|
|
|
|
/*
|
|
* BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no
|
|
* SPD and no SPM, as they are the only ones that can be used as BL32.
|
|
*/
|
|
#if !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME)
|
|
# if defined(SPD_none) && !ENABLE_SPM
|
|
# undef BL32_BASE
|
|
# endif /* defined(SPD_none) && !ENABLE_SPM */
|
|
#endif /* !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME) */
|
|
|
|
/*******************************************************************************
|
|
* FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
|
|
******************************************************************************/
|
|
#define BL2U_BASE BL2_BASE
|
|
#define BL2U_LIMIT BL2_LIMIT
|
|
|
|
#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
|
|
#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000)
|
|
|
|
/*
|
|
* ID of the secure physical generic timer interrupt used by the TSP.
|
|
*/
|
|
#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
|
|
|
|
|
|
/*
|
|
* One cache line needed for bakery locks on ARM platforms
|
|
*/
|
|
#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
|
|
|
|
/* Priority levels for ARM platforms */
|
|
#define PLAT_SDEI_CRITICAL_PRI 0x60
|
|
#define PLAT_SDEI_NORMAL_PRI 0x70
|
|
|
|
/* ARM platforms use 3 upper bits of secure interrupt priority */
|
|
#define ARM_PRI_BITS 3
|
|
|
|
/* SGI used for SDEI signalling */
|
|
#define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0
|
|
|
|
/* ARM SDEI dynamic private event numbers */
|
|
#define ARM_SDEI_DP_EVENT_0 1000
|
|
#define ARM_SDEI_DP_EVENT_1 1001
|
|
#define ARM_SDEI_DP_EVENT_2 1002
|
|
|
|
/* ARM SDEI dynamic shared event numbers */
|
|
#define ARM_SDEI_DS_EVENT_0 2000
|
|
#define ARM_SDEI_DS_EVENT_1 2001
|
|
#define ARM_SDEI_DS_EVENT_2 2002
|
|
|
|
#endif /* __ARM_DEF_H__ */
|