242 lines
6.9 KiB
C
242 lines
6.9 KiB
C
/*
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* Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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#include <arm_def.h>
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#include <board_arm_def.h>
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#include <board_css_def.h>
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#include <common_def.h>
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#include <css_def.h>
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#if TRUSTED_BOARD_BOOT
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#include <mbedtls_config.h>
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#endif
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#include <soc_css_def.h>
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#include <tzc400.h>
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#include <v2m_def.h>
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#include "../juno_def.h"
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/* Required platform porting definitions */
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/* Juno supports system power domain */
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2
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#define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \
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JUNO_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \
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JUNO_CLUSTER1_CORE_COUNT)
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/* Cryptocell HW Base address */
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#define PLAT_CRYPTOCELL_BASE 0x60050000
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/*
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* Other platform porting definitions are provided by included headers
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*/
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/*
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* Required ARM standard platform porting definitions
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*/
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#define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT
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/* Use the bypass address */
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#define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET
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/*
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* Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB
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* in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of
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* flash
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*/
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#if TRUSTED_BOARD_BOOT
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#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000
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#else
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#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000
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#endif /* TRUSTED_BOARD_BOOT */
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/*
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* If ARM_BOARD_OPTIMISE_MEM=0 then Juno uses the default, unoptimised values
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* defined for ARM development platforms.
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*/
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#if ARM_BOARD_OPTIMISE_MEM
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/*
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* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
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* plat_arm_mmap array defined for each BL stage.
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*/
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#ifdef IMAGE_BL1
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# define PLAT_ARM_MMAP_ENTRIES 7
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# define MAX_XLAT_TABLES 4
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#endif
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#ifdef IMAGE_BL2
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#ifdef SPD_opteed
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# define PLAT_ARM_MMAP_ENTRIES 11
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# define MAX_XLAT_TABLES 5
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#else
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# define PLAT_ARM_MMAP_ENTRIES 10
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# define MAX_XLAT_TABLES 4
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#endif
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#endif
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#ifdef IMAGE_BL2U
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# define PLAT_ARM_MMAP_ENTRIES 4
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# define MAX_XLAT_TABLES 3
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#endif
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#ifdef IMAGE_BL31
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# define PLAT_ARM_MMAP_ENTRIES 7
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# define MAX_XLAT_TABLES 3
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#endif
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#ifdef IMAGE_BL32
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# define PLAT_ARM_MMAP_ENTRIES 5
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# define MAX_XLAT_TABLES 4
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#endif
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/*
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* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
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* plus a little space for growth.
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*/
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#if TRUSTED_BOARD_BOOT
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# define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000
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#else
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# define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000
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#endif
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/*
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* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
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* little space for growth.
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*/
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#if TRUSTED_BOARD_BOOT
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#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
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# define PLAT_ARM_MAX_BL2_SIZE 0x1E000
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#else
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# define PLAT_ARM_MAX_BL2_SIZE 0x1A000
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#endif
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#else
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# define PLAT_ARM_MAX_BL2_SIZE 0xC000
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#endif
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/*
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* PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a
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* little space for growth.
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* SCP_BL2 image is loaded into the space BL31 -> BL1_RW_BASE.
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* For TBB use case, PLAT_ARM_MAX_BL1_RW_SIZE has been increased and therefore
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* PLAT_ARM_MAX_BL31_SIZE has been increased to ensure SCP_BL2 has the same
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* space available.
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*/
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#define PLAT_ARM_MAX_BL31_SIZE 0x1E000
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#if JUNO_AARCH32_EL3_RUNTIME
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/*
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* PLAT_ARM_MAX_BL32_SIZE is calculated for SP_MIN as the AArch32 Secure
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* Payload. We also need to take care of SCP_BL2 size as well, as the SCP_BL2
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* is loaded into the space BL32 -> BL1_RW_BASE
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*/
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# define PLAT_ARM_MAX_BL32_SIZE 0x1E000
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#endif
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/*
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* Since free SRAM space is scant, enable the ASSERTION message size
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* optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40).
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*/
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#define PLAT_LOG_LEVEL_ASSERT 40
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#endif /* ARM_BOARD_OPTIMISE_MEM */
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/* CCI related constants */
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#define PLAT_ARM_CCI_BASE 0x2c090000
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#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4
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#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3
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/* System timer related constants */
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#define PLAT_ARM_NSTIMER_FRAME_ID 1
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/* TZC related constants */
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#define PLAT_ARM_TZC_BASE 0x2a4a0000
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#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT))
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/*
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* Required ARM CSS based platform porting definitions
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*/
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/* GIC related constants (no GICR in GIC-400) */
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#define PLAT_ARM_GICD_BASE 0x2c010000
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#define PLAT_ARM_GICC_BASE 0x2c02f000
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#define PLAT_ARM_GICH_BASE 0x2c04f000
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#define PLAT_ARM_GICV_BASE 0x2c06f000
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/* MHU related constants */
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#define PLAT_CSS_MHU_BASE 0x2b1f0000
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/*
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* Base address of the first memory region used for communication between AP
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* and SCP. Used by the BOM and SCPI protocols.
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*/
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#if !CSS_USE_SCMI_SDS_DRIVER
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/*
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* Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which
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* means the SCP/AP configuration data gets overwritten when the AP initiates
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* communication with the SCP. The configuration data is expected to be a
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* 32-bit word on all CSS platforms. On Juno, part of this configuration is
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* which CPU is the primary, according to the shift and mask definitions below.
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*/
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#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80)
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#define PLAT_CSS_PRIMARY_CPU_SHIFT 8
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#define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4
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#endif
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/*
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* PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
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* SCP_BL2 size plus a little space for growth.
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*/
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#define PLAT_CSS_MAX_SCP_BL2_SIZE 0x14000
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/*
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* PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current
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* SCP_BL2U size plus a little space for growth.
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*/
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#define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x14000
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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CSS_G1S_IRQ_PROPS(grp), \
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ARM_G1S_IRQ_PROPS(grp), \
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INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
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/*
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* Required ARM CSS SoC based platform porting definitions
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*/
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/* CSS SoC NIC-400 Global Programmers View (GPV) */
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#define PLAT_SOC_CSS_NIC400_BASE 0x2a000000
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#endif /* __PLATFORM_DEF_H__ */
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