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Manoj Kumar 7428bbf443 n1sdp: fix DMC ECC enablement sequence in N1SDP platform 
The DMC-620 memory controllers in N1SDP platform has to be put
into CONFIG state before writing to ERR0CTLR0 register to enable
ECC.

This patch fixes the sequence so that DMCs are set to CONFIG
state before writing to ERR0CTLR0 register and moved back to
READY state after writing.

Change-Id: I1252f3ae0991603bb29234029cddb5fbf869c1b2
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
 		2019-07-23 10:54:14 +01:00
..
aarch64 Rename Cortex-Ares to Neoverse N1 2019-02-19 13:50:07 +00:00
include n1sdp: add code for DDR ECC enablement and BL33 copy to DDR 2019-06-26 14:07:51 +01:00
n1sdp_bl31_setup.c n1sdp: fix DMC ECC enablement sequence in N1SDP platform 2019-07-23 10:54:14 +01:00
n1sdp_def.h n1sdp: fix DMC ECC enablement sequence in N1SDP platform 2019-07-23 10:54:14 +01:00
n1sdp_interconnect.c plat/arm: Introduce the N1SDP. 2018-10-29 17:50:31 +05:30
n1sdp_plat.c n1sdp: add code for DDR ECC enablement and BL33 copy to DDR 2019-06-26 14:07:51 +01:00
n1sdp_security.c plat/arm: Introduce the N1SDP. 2018-10-29 17:50:31 +05:30
n1sdp_topology.c plat/arm: Sanitise includes 2019-01-25 16:04:10 +00:00
platform.mk n1sdp: add code for DDR ECC enablement and BL33 copy to DDR 2019-06-26 14:07:51 +01:00