9f7bab42a1
We now have code to detect the CPU topology at runtime, and can also populate the CPU nodes in a devicetree accordingly. This is used by the ARM FPGA port, for instance. But also a GICv3 compatible interrupt controller provides MMIO frames per core, so the size of this region needs to be adjusted in the DT, to match the number of cores as well. Provide a generic function to find the GICv3 interrupt controller in the DT, then adjust the "reg" entry to match the number of detected cores. Since the size of the GICR frame per cores differs between GICv4 and GICv3, this size is supplied as a parameter to the function. The caller should determine the applicable value by either hardcoding it or by observing GICR_TYPER.VLPIS. Change-Id: Ic2a6445c2c5381a36bf24263f52fcbefad378c05 Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
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| .. | ||
| tbbr | ||
| asm_macros_common.S | ||
| bl_common.h | ||
| bl_common.ld.h | ||
| debug.h | ||
| desc_image_load.h | ||
| ep_info.h | ||
| fdt_fixup.h | ||
| fdt_wrappers.h | ||
| image_decompress.h | ||
| interrupt_props.h | ||
| nv_cntr_ids.h | ||
| param_header.h | ||
| romlib.h | ||
| runtime_svc.h | ||